[DRC NSTD-1] and [DRC UCIO-1] when generating bitstream with HDMI on Zybo

[Maciej Piechotka]

I'm trying to use HDMI port on my Zybo board. On Vivaldo 2017.2 I run into problems when generating bitstream:

[DRC NSTD-1] Unspecified I/O Standard: 3 out of 141 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hdmi_in_ddc_scl_io, hdmi_in_ddc_sda_io, and hdmi_in_hpd_led_tri_io[0].

[DRC UCIO-1] Unconstrained Logical Port: 11 out of 141 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: hdmi_in_ddc_scl_io, hdmi_in_ddc_sda_io, hdmi_in_data_p[2:0], hdmi_in_data_n[2:0], hdmi_in_clk_n, hdmi_in_clk_p, and hdmi_in_hpd_led_tri_io[0].

How should I specify correct constraints? What have I done wrong (i.e. why they aren't specified automatically)?

[jpeyron]

Hi @Maciej Piechotka,

I have adjusted the xdc to work with your above wrapper and attached it below.

cheers,

Jon

zybo.xdc

[artvvb]

@Maciej Piechotka

Could you clarify if you are trying to use one of our Zybo HDMI demos, or creating your own project? If the latter, it would be helpful to know what the top level of your design and your constraints look like.

Thanks,

Arthur

[Maciej Piechotka]

My own project. Strangely it happens when I drag'n'drop 'HDMI In' connector from the 'Board' panel. If I create manually connector named 'DDC' the warning is gone.

[jpeyron]

Hi @Maciej Piechotka,

I will reach out to the creator of the DVI2RGB source IP in the morning to see if we decided not to constrain the pins they way we do with most of the other drag an drop selections. My guess is that it is due to the multiple ways it can be connected. I added a screen shot of a projects block design that generates a bitstream along with the xdc file. 

cheers,

Jon 

zybo.xdc

[jpeyron]

Hi @Maciej Piechotka,

Unfortunately, I was not able to talk to the creator of the IP on Tuesday or yesterday. They are out of the office the rest of this week. I will be able to get a response for you next week.

thank you and sorry about the delay,

Jon 

[Maciej Piechotka]

@jpeyron Any progress?

It doesn't seem to work even with attached constraints:

[DRC UCIO-1] Unconstrained Logical Port: 8 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: hdmi_in_data_p[2:0], hdmi_in_data_n[2:0], hdmi_in_clk_n, and hdmi_in_clk_p.

 

[jpeyron]

Hi @Maciej Piechotka,

Could you please attach your block design and wrapper file so we can better assist you with your constraint issues? 

thank you,

Jon

 

[Maciej Piechotka]

@jpeyron I've attached tcl and wrapper. Please let me know if you need something else.

test.tcl

test_wrapper.v

[Maciej Piechotka]

@jpeyron Thanks. That one seems to work for simple designs but for more complicated designs it seems to place clocks in incorrect positions but I start separate thread for it.

[jpeyron]

Hi @Maciej Piechotka,

In the clocking wizard i click into clocking options. Under Primitive i change from MMCM to PLL and I am able to generate a bitstream with your project.

cheers,

Jon

[Maciej Piechotka]

@jpeyron Thanks. Using Zynq PS worked as well.