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gutielo

[Zedboard] XADC + Xillybus not working properly

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(Not sure if this thread should go in Embedded Linux. If so, please feel free to move it)

Hello everyone. I'm having quite a hard time trying to make these two (XADC and Xillybus/Xillinux) work together and I was hoping someone here could lend me a hand.

Basically, what I am trying to achieve is: I'll input some analog signals to VP/VN, Vaux0 and Vaux8 to the XADC. I want it to convert them and that conversion to be written to a FIFO that can be read by Xillybus, which will make it available for me in Xillinux (so with a simple command I can dump the conversion into a file). A more visual way to explain this would be:

conexiones.png.a28862c7072ca938cfbf041bb8a277c0.png.7f5b4a35c428d5e20ef40d368477c69d.png

Problem: I am getting nothing but zeros from Xillybus. How am I collecting this data? Xillinux comes with a few demo apps. I've modified one of them (streamread.c) so I can write whatever is reading to a file. So I connect to Xillinux via SSH and run this:

touch output
./streamread /dev/xillybus_datastream output

This output keeps getting bigger as long as streamread is running but as I said, there's nothing but 0000000...

Info: I generated the XADC using the wizard so I guess everything is properly instantiated.

Tests I've run so far:

  • I've tried the XADC and Xillybus separately and they both work just fine. For the XADC, I followed this tutoral here and I managed to get readings from all inputs (and even temperature!) in spite of the fact that I wasn't even feeding it (all it was reading was noise). As for Xillybus, I tried a loopback FIFO where I could write something in the terminal and see it in a different one, so that worked good as well.
  • Since XADC outputs 16-bit data, I had to create a new Xillybus project (I made it using the IP Core generator they have built in their website) to add a 16-bit-wide FIFO (actually, they had to be 2 since one is from host to FPGA and the other one from FPGA to host, although I'm only interested in the latter). I updated Xillybus accordingly and tested it by creating a simple VHDL that would send some characters to the FIFO if switch 1 was high. Worked like charm. I even used ./streamread /dev/xillybus_datastream output to make sure streamread was working properly and it was.
  • This one I can't understand why is happening, but it's happening. I modified my VHDL code and used 4 LEDs of the Zedboard to see if the XADC was working good. So I took the last 4 bits of the conversion of the XADC and associated them with one LED each (LED0 with dout(0), LED1 with dout(1), and so on). They never turned on so the XADC was outputting zeros or it wasn't working at all. So I decided to do this: DRDY signal from XADC = LED1 and EMPTY flag from FIFO = LED2. LED1 was turned off the whole time (XADC wasn't converting) but to my surprise, EMPTY flag was always 1. I mean, that makes sense, if DRDY is never 1, it can't write to the FIFO (cause that DRDY acts as the wr_en for the FIFO) but then how am I getting so many zeros in Xillinux when using streamread? Isn't Xillybus supposed to not read from the FIFO if the EMPTY flag is high?

I don't know what else to try, really. Hope you can guide me through this. If you need any more info like source code or something, I will gladly share it.

Thank you (and sorry for the long post :wacko:)

Edited by gutielo

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2 answers to this question

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Hi @gutielo,

Unfortunately, I do not have any experience with Xillybus. Have you tried reaching out to Xillybus support here? Hopefully a more experienced community memeber will have some input for you.

cheers,

Jon

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Thank you! I already got it working, although I'm getting some weird values from the XADC now. I'll make a new thread about it and see if you guys know something.

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