Want to rework Arty board so Bank 14 is 1.8V

[Paul_kimelman]

I want to rework some Arty boards so bank 14 is 1.8V vs. 3.3V. I had planned a simple tying of a patch wire from C71 high side (1.8V) to C21 (or one of the others in C21 to C29 decap set). That is easy. But, I cannot see where the trace is that feeds C21 to C29 and so the bank 14 balls. There is no trace showing on bottom (where the caps are) nor on top (where there are what I assume are plated through-holes (covered in white paint, so hard to tell)). I am unsure if this means a 3.3V plane/layer on board but if so, I do not see where it is going. It seems unlikely you would use blind/buried via on such a simple board, so I am mystified. 

Can someone from Digilent explain the routing for that one power net so I can see if a rework is possible. I had assumed it would just be a trace cut, but I cannot see which trace that would be if so.

Thanks, Paul

P.S. Seems pretty crazy to still not have 1.8V as a bank option given how common 1.8V has become.

[jpeyron]

Hi @Paul_kimelman,

I have reached out to our layout engineer about your questions and will respond here when I get a response.

cheers,

Jon

[Paul_kimelman]

Thanks Jon.

[Paul_kimelman]

Hi Jon. Any feedback from the layout guy? Thanks, Paul

[jpeyron]

Hi @Paul_kimelman,

I heard back from out layout engineer. Unfortunately, there is no feasible way to do this.  3V3 is a plane that connects to three banks on the FPGA.  There would be no way to isolate just Bank 14. If you take a look at sheet 7 on the schematic, you can see the bank 14 power pins.  Since this is a ball grid array, there is no access to these pins as they are all underneath the chip itself. And just in case.  Powering the whole plane at 1v8 would cause many other problems as many of the other ICs on the board connect to the 3V3 plane too. He suggest you use a level shifting Pmod(here) on JC or a level shifting Shield to convert those signals to your desired voltage.

 

thank you,

 

Jon

 

[Paul_kimelman]

Wow, that is really a shame. I realized I could not access the balls, but normally you can just use the decoupling caps that connect to the balls. I was afraid of this that he used a power plane. Sigh. 
The level shifter is not feasible since the pin involved is bi-directional and so a level shifter is not feasible (for any kind of speed anyway). In theory I could treat as unidirectional and wire OR on the 1.8V side, but that may be too messy. I will have to consider this. Thanks.
I do think you guys need to consider that 1.8V is becoming far more common. A spin of this board could have a post to feed one or both of the general banks, using a trace instead of the 3.3V plane (or using a split V plane). Given the decap sizes, I suspect that you are not carrying that much current, although bank 15 seems to be assuming a lot more noise given the extra decap C.

Thanks, Paul

[Paul_kimelman]

I should have been clearer: your level shifter board is not feasible because you made the DIR lines only available by switch and not by FPGA pin. That is really sad because if the FPGA could control direction then this would work fine.
Do you know if anyone has a PMOD which already does this? Else I will have to spin a small board myself I guess.