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DVI Receive on Zybo


vadim

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Hello, 
I figured I'd leave the GoPro thread alone and start a new, independent one. I am a new owner of a Zybo board that I received from Digilent yesterday - order 2014-194227. Very excited to test my design with this board.I am using Vivado for development, and was able to get the included HDMI TX design to work properly. However, my real interest is receiving DVI/HDMI images. Is there an equivalent HDMI Rx IPI block for Vivado that can be used? I'm trying to get a handle on how much needs to be changed to port xapp495 to Zynq/7-series. Things like the gearbox are not necessary. However, the phase detector in xapp495 had some dedicated HW support in the S-6 SERDES, while the 7-series SERDES lacks this, so it would need to be built in logic. An example, even if it's "raw", would be extremely useful.

 

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Actually, all that happened was that for some reason Vivado was not passing in the "artix7" generic to the ISEREDE2 logic appropriately, and the tools were complaingning they didn't know what a "ISERDES2" was - which was for Spartan6 only. The generic was set to artix7 correctly, not sure what happened, but I commented out the S-6 code and changed nothing else, and it worked. 

 

So far the only problem I'm having is simulating the GoPro-derived DVI Receive core. The phase alignment block appears not to work, and the datapath fails. The DVI Transmit core used for simulation is known working, and produces a proper encoded TMDS set of signals.

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Hey Vadim,

 

We're working towards a library of Vivado IP Integrator cores for our 7 series boards which will include HDMI RX and TX cores. Once it gets completed we'll give a shout out on the forum.

 

For now, the GoPro project has some IP you will find useful. The only bummer here is that the project is in EDK and not Vivado. The hdmi_rx core does exactly what you described, and is essentially a port of XAPP495 to 7 series. It shouldn't be too much work to wrap it up in a Vivado core so that it can be used in your project.

 

By the way, you will likely need to modify the EDID packet, which is defined in the SDK software. We had to play with it quite a bit to make it work properly with the GoPro, and I'm not certain it will look proper to a standard computer. I recommend using Phoenix EDID editor (awesome software!) to clone one of your computer monitors EDID and trying that.

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Hi Sam,

 

Thanks for the quick response. I guess I'll grab that pcore and construct my peripheral out of it. Are there testbenches you found useful when that was being created?

 

Also, I've got some EDID tables saved off. I've had success with Analog Devices' EEdit as well. At the risk of getting stuff "thrown" at me, any idea when there might be a release of the Vivado support stuff for Zybo? In all seriousness, this the cheapest fully-functional Zynq solutions out there, microzed has less features for more cost, so Vivado support would be very popular with users. But, I suppose you probably knew that already...

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I've been doing a bit of playing around with DVI-D lately (see http://hamsterworks.co.nz/mediawiki/index.php/HDMI_Input) on Spartan 6, so if you are desperate to get started maybe it will help.

 

The source project should easily port through to Vivado, but I haven't started looking at the 7-series SERDES to see how hard it will be to tweak the "input_serailizer.vhd" and the required clocking. It might just work :-)

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Actually I had a look at the schematics can somebody explain how it works as a dual-mode (source or sink) interface?

 

From the '7-series FPGA SelectIO resources' - "The TMDS standard requires external 50Ω pull-up 

resistors to 3.3V on the inputs. TMDS inputs do not require differential input termination 
resistors."
 
I read this to be the same as with the Spartan-6 series (and other CML) where the source should not have any termination resistors.
 
post-35-0-22889200-1413511038_thumb.jpg
 
(Picture snipped from the "Spartan-6 SelectIO Resources" pdf)
 
Won't the termination be wrong if the port is used as an source, as it will be terminated twice, once at the source and once at the sink?
 
post-35-0-78040400-1413511363_thumb.jpg
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@hamster: Double-termination might lower the impedance to the diff pair, and the driver may not like that very much... I'll model the source/sink terminated interface over the weekend and see what happens to the signal, going from a Zynq TMDS 3.3V driver, through the DVI connector, into a Zynq TMDS 3.3V receiver. IBIS models for all this exist, so  this is not hard to construct.

 

I had some success getting the testbench from here - https://eewiki.net/pages/viewpage.action?pageId=15925278#VGAController(VHDL)-CodeDownloads - I took their two modules and wrapped them in a testbench that can drive any arbitrary DVI receive circuit with legit image data that's properly framed. The image itself is just pixels toggled all high/low for the 3 colors.

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Hi vadim,

 

Actually, would you mind if you summarized your answer here on the forum? That way other people who encounter the same issue but need a little more guidance on how to resolve the problem can find out here. You don't have to if you don't want to though.

 

Thanks,

James

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