Basys3 sine wave simulation

[Hendrik]

I have created a FIR filter and would like to run a simulation using  sine wave tones at different frequencies to verify the filter frequency response.Any idea how I can do this within Vivado?

Thanks

H

[D@n]

@Hendrik,

It depends on how good you want your sine wave to be.

The easy answer would be to start with this technique for tracking phase, and then to use the top several bits of the phase register/accumulator as an index into a sine wave lookup table. 

The problem with that solution is that it can be expensive in table size if you want to create a really high quality sine wave.

The next best technique is to use a CORDIC algorithm to generate the sinewave.  The CORDIC approach can be used to make a sinewave just about as good as you want it to be.  It's a touch more complicated than the table lookup though, so if you aren't familiar with how to do this I'd start with the table first.

Dan

[artvvb]

@Hendrik

You can find a fairly detailed walkthrough of how to do the first method D@n mentions here: http://www.instructables.com/id/Digilent-Pmod-R2R-Sine-Wave-Generator/

The instructable is also trying to talk through how to do vivado block design with custom verilog modules, so some of the steps may be irrelevant to you.

Hope this helps,

Arthur

[artvvb]

@Hendrik

Another resource: This project description contains a block design overview and another good explanation of the wave-table method, including the ability to change the frequency of the wave.

[Hendrik]

Hi Arthur ,thanks for the info.

Another quick question since I am not able to get a good example.Do you know how to generate a test tone(sine wave) in Vivado?I assume I can create a test bench to do this. I want to feed a test tone say at 1KHz into the XADC  of the Basys3 and view the FIR output.Next step is to increase the tone frequency with 1 KHz ,now the test tone is at 2KHz...repeat this process up to 18 KHz. In short how do I simulate analog signals in Vivado.

The real test would be to connect the waveform generator to the header and measure output of the R2R DAC.

 

Thanks

Hendrik

 

[D@n]

@Hendrik,

Why do this with "Vivado"?  Forgive me for my open sourcerer ways, but ... wouldn't you rather build something that you could reuse later with a different vendor's solution?  Verilog and VHDL are both fairly vendor independent.  Further, if you use Verilog, you can simulate your entire design using Verilator without needing any license or proprietary IP.  Then, when you are ready to actually implement your design on your device, you'll already know it works.

Dan

[D@n]

As a follow up to some of my previous comments, I've now posted some articles describing much of how to do this on ZipCPU.com. 

One topic I've addressed includes how to generate a sine wave.  The examples provided are generic Verilog solutions, so they should work across all versions of Vivado.  (As well as across FPGA vendors.)   Examples include how to calculate a sine wave from a table, how to calculate a sine-wave from a quarter wave table, how to generate a sine wave using a CORDIC, how to tell if these algorithms work, etc.

Another topic discussed includes how to build a generic FIR filter in Verilog.  I'm still working on articles showing how to test such a filter.  I'd also like to post about how to build a filter that operates on data that comes in every N clocks--I just haven't gotten that far yet.

Dan