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Vivado filter project



I'm new in FPGA and I'm trying to realize a filter using the FPGA Nexys 4 on Simulink. I have already done the Simulink circuit and export it to the Vivado Design sout as a project. Here I choose the right FPGA but i have problem with I/O Ports planning. My output of this project will be a filter which will realize the filtration of biological signal (ECG) which i will bring on JXAD input port on FPGA.

Can somebody please help me with realization in Vivado and tell me, which output can be the best after the filtration? 

Your help means very much to me...



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Welcome to the forums, and the wonderful world of FPGA design!  Sounds like you have a wonderful application to work on, and I wish you well on your project.

Two quick items: First, there aren't that many people on this forum that do work with Simulink.  (Sorry)  You might want to try your question again on a simulink forum.  Second, I'm not sure I understand your question.  Can you explain what you mean by, "i have problem with I/O Ports planning", and "which output can be the best after the filtration"?

I know that assigning I/O wires to a particular port usually takes place via an XDC file when using Vivado.  I don't know, though, how Simulink generates such a file, or if it doesn't generate the file then how you interact with it and generate your own.  Sorry.


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I realize that this reply isn't an answer to Dimitry's question but my understanding is that the Project Vault is for presenting working projects. Requests for help with using tools should be presented in the FPGA forum.

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