Cmod S6 reset

[nixiebunny]

Hi. Experienced EE here. I am designing a Cmod S6 module into a radio telescope controller PC board, since it's easier than making my own FPGA support circuitry.

I need to ensure that the controller comes up in a safe state, since it commands the telescope's secondary mirror to move. I cannot find any reset signal in the VHDL file top.vhd, which would allow me to initialize the state of my controller.

Do I need to add my own power-on reset IC to my PC board to provide this function?

 

[D@n]

Hi @nixiebunny!  Welcome to the forum.

I'm not sure where you are getting the top.vhd from.  I do all my S6 programming in Verilog. 

As for starting up in a known state, Xilinx allows you to specify the initial value of any register variables.  In Verilog, this looks like "initial register_name = 0;" ... or whatever value you'd like to set it to.  This also works for any registers controlling output values.  Further, as part of the startup sequence, Xilinx chips hold all of their output pins in a high impedence state (neither 1 nor 0) until the configuration completes.  At that time, any initial values have been set and initial output values can be sent.

You can also either of the buttons (or a GPIO for that matter) to reset relevant portions of your design if you would like.  I used one of the buttons to reset the CPU I placed into my design if it ever got ... stuck. 

Dan