PModAD1 documentation

[riche]

I followed the tutorial at https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start with PmodAD1 and got it all working. I was confused until I saw this post 

that says to use 50MHz for ext_spi_clk and that it only works with 1 channel.

However, I'm looking for more information and I'm probably just not looking in the right place. For example, is the RTL available for PmodAD1_v1_0? Also, how is the ext_spi_clk and the SClk pin related? Is there any buffering of the samples? Also, is there any documentation that comes with the sample code?

Thanks

[D@n]

@riche,

I didn't see the 50MHz clock reference, but the data sheet for the A/D on the PMod AD1 says that the maximum SCLK rate is 20MHz.

Incidentally, the PMod AD1 uses the same A/D as the PMod MIC3.  As I understand the limitations of the canned demo, you might find it easier to modify a piece of regular open source Verilog, written for the MIC3, than to use the canned demo to get both samples out, synchronously.  The open source solution has an optional integrated FIFO, of a parameterizable length, as well.  Oh, and it's also got an open source simulation model (sine wave input) that you can use to test/prove that your interface works.

Just a thought.

Dan

[Notarobot]

@riche

The post you refering to has links to information and even actual project demoing PmodAd1.

The Digilent github version makes possible to use only one A/D converter chip while the board is capable to run two ADC in parallel. However, the post included a link to a different version which runs two.

In order to run ADC chip you should send to Pmod the chip select signal - CS to start the conversion and a clock signal - SCLK. It takes about 20 clock cycles to complete the conversion. So for 1 MHz conversion rate you would need CS at 1 MHz and SCLK at 20 MHz. However, PL code typically has internal counter = frequency divider which is used to control state machine. In result the input frequency is higher. There are several versions of HDL code for Pmod-AD1: Analog Devices (verilog), Digilent - 2 versions (VHDL) and Hamster (VHDL). By changing the clock frequency you can control the AD conversion rate.

I am not aware of detailed description of the demo. I assume that user should read the datasheets for AD7476 and try to understand available code.

Good luck!

[riche]

Thanks for the input. So no documentation for the "canned demo" from the vivado-library-master.zip used in the tutorial referenced above. That's not a very useful demo. I'll look at the other implementations. Thanks.

 

[Notarobot]

Hi riche,

Could you please, explain what documentation do you expect. You can always ask question if you need clarification.

This area is very dynamic, everything is in constant move. That explains why some tutorials are getting obsolete and difficult to follow.

Thanks

[jpeyron]

Hi @riche,

We encourage suggestions and feedback for our products/documentation. We are always looking to improve. Please keep in mind that we are a small company that is staffed as such.

cheers,

Jon