ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:clk_wiz:5.2

[Lisset]

I am using Vivado 2017.1 and I got the following error with the create_project.tcl for tutorial Getting Started with ARTY's Base System Design for Arty Artix 7.

 

ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:clk_wiz:5.2 
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 clk_wiz_1 "
(procedure "create_root_design" line 113)
invoked from within
"create_root_design """
(file "../src/bd/system.tcl" line 899)

while executing
"source $origin_dir/src/bd/system.tcl"
(file "./create_project.tcl" line 103)

 

Can somebody advise me how to fix it?

[jpeyron]

Hi @Lisset,

This project is made to work with Vivado 2016.4. I was able to get it to work in Vivado 2017.1 with a work around by going in to \Arty-BSD-master\src\bd\system\hw_handoff and editing the version from 2016.4 to 2017.1. Then after launching the project using the tcl script you will need to update the IP's. After this is done you should re-validate the project in the block design to make sure it is good. Then you will need to create a wrapper and generate a bitstream. I have attached my project in Vivado 2017.1. I did not verify anything in sdk but was able to generate a bitstream in vivado 2017.1.

cheers,

Jon

Arty-BSD-master.zip