SPI Slave Select Examples, or 2nd SPI port?

[RichardV]

Hello. I was able to follow the example "How To Store Your SDK Project in SPI Flash". My new problem is that I want to drive a second SPI device using that QSPI port. Should I share that existing QSPI port with my new external slave device, or implement another AXI_Quad_SPI block?

Now I'm forced to ask, how does Vivado (or SDK) know where the MISO, MOSI, SCLK and Slave Select lines are for the memory device? Vivado generated an XDC file with only one line ("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"), yet it works just fine to download from the external flash memory (CMod-A7 board). There must be another file that has this board information. I'm calling this an "invisible constraint file".

Do I use the actual constraint file to set my SPI port pin assignments for my second port? If so, wouldn't that "invisible constraint file" interfere?

If recommended to use 1 SPI port to drive the 2 slaves, then how do I implement the Slave Select signals? Are there any SPI examples with multiple slaves to demonstrate this?

Thank you, Richard V

[jpeyron]

Hi @RichardV,

The board files constrain the internal components on the board. Here is part of what the board files look like for the Cmod A7. If you look at the schematic here on page 2 you will see that the IC3 does not have access to external pins. You will need to use another quad spi port, with an xdc file, that is connected to external pins. We have a Pmod SF3 that programs flash that might be helpful to what you are doing here.

cheers,

Jon

[RichardV]

Hello again Jon. Thank you for this information, and all of your help.

I also realized that the Flash Memory is a Quad SPI, so it's not compatible with the settings for my standard SPI devices. Yes, I realize that tapping into those SPI lines on IC3 was going to be difficult. Thank you for pointing out the PMOD port, which is accessible.

Thank you for that SF3 example too! This is a big help.

Best regards, Richard V

[RichardV]

Hello one last time on this subject Jon. I just visited the repository with that SF3 example. The whole project is in pieces. I see multiple version of constraint files, and I don't see a Vivado project anywhere. I don't understand how to use this repository too. It's not like Github. What does "Pull" mean? How do I download a project as a complete entity that I don't have to reconstruct?

I visited that repository "Boot Camp", but it also isn't very clear. Can you offer some suggestions on how to get started with this complicated tool (Vivado & SDK)?

Thank you, Richard V

[jpeyron]

Hi @RichardV,

Sorry about not including this. To use the IP's you need to download the vivado-library here. When making a project you will need to first go to project settings->ip->manage ip repository and include the whole vivado library folder. Here is a tutorial that will be updated in the near future but should still be helpful.

cheers,

Jon

[RichardV]

Thank you Jon. This is very helpful.

I found that one has to click that "Code" tab or the "Download/Clone" option won't show up.

Regards, Richard V

[RichardV]

Hello again Jon. I am trying to follow along with the PmodSF3 example. Unfortunately my block does not validate because I have all of these port input pins left open (warnings). I cannot synthesize my design, even though the Validate function show only warnings. There is no example explaining what ports need to be connected.

When I dropped in an AXI_QUAD_SPI block the Automated Connection created an SPI port for me. The PmodSF3 block did not do this.

What I don't understand is how am I supposed to create an SPI port with MOSI, MISO, SCLK and CS signals? I know how to enter these arbitrary names into a constraint file, but I don't understand how to make these Pmod pins take over that function.

Another problem arises when I can finally get into SDK. I don't know what KEYWORDS to use to make the connections between those constraint file names and what SDK is expecting.

Is there a tutorial showing how to connect an SPI port from start to finish? I have worked with SPI ports for many years with Microcontrollers, so this FPGA IP approach is totally new to me. Is there an Primer I can follow?

Thank you, Richard V

 

 

[jpeyron]

HI @RichardV,

I have attached a project in vavado 2016.4 with the cmod A7 and the PmodSF3 using JA. The sdk code is not 100% working but the block diagram is how you would connect it. If you are wanting to use different I/O pins other than JA then you would make the Pmodout external and constrain them with an xdc file. I know we are in the process of fixing the PmodSF3 IP core but we do not have an ETA. Here is a forum that discusses the PmodSF3. The project i attached has the main.c, PmodSF3.h and PmodSF3.c whihc a few changes from the forum thread I linked to which is closer.  Also here is a tutorial about IP's that is going to be updated in the near future.

cheers,

Jon

PmodSF3.zip

[RichardV]

Hello Jon. I got that PmodOLED_v1_0 example working using the IP provided in the "vivado-library-master" library file. I have an OLDED module, so I was able to verify it works just looking at the demo run. I have a bigger problem though; I need to avoid using those IP blocks.

I see your PmodSF3 example does a similar thing in using an IP block. Now this "IP" itself is the problem. It's not truly a good example to follow if one wants to use the AXI_QUAD_SPI block. There is a coding concept called "data hiding" that IP blocks seem to employ, which is exactly why I can't use them.

I cannot use "Intellectual Property" code for my final product. I looked at the block diagram settings for them, but I cannot access the lowest level of this block diagram design. It does not use the standard constraint file that I can view, and it doesn't show how to use the SPI port with SDK (where are are MOSI, MISO, SCLK and CS defined in the code?).

So I am back where I started trying to get that AXI_QUAD_SPI block to work with an external SPI device, but NOT using an IP block. I believe that it must be possible. Please direct me to the literature that I need to read to accomplish this?

Thank you, Richard V

[jpeyron]

Hi @RichardV,

Here is a forum thread that might be useful for setting up the axi quad spi. Here is the AXI Quad SPI v3.2 LogiCORE IP Product Guide. I believe when you add the axi quad spi to your block design you can right click on it and run an xilinx made IP example to see how it is used.

cheers,

Jon