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Zedboard Zynq 7000 XADC Header


Sam Bergami

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@jpeyron our issue must have stemmed from our voltage source. After switching to Waveforms like you suggested above, the readings in the terminal no longer jump randomly. They are now consistent and accurate with the difference between our input voltages.

Thanks so much for your help!

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Sorry for bothering you again guys, but I haven't been able to make it work. I'll try to explain what I've done so far and I'd really appreciate if any of you could shed some light on the problem. This is what my project looks like:

conexiones.png.a28862c7072ca938cfbf041bb8a277c0.png

I have run separate tests on the XADC and Xillybus, meaning that I created a testbench for the XADC which worked correctly and I also used the loopback fifo (width: 8 bits) that comes installed by default with Xillybus. So I put it all together and created a new Xillybus using their website to include 2 new fifos (one of them I won't be using it but it was required to create 2) that were 16 bits wide. I use the drdy signal from XADC as wr_en for the fifo and the output from the XADC is the data_in of the FIFO.

I am writing the output of the fifo using the streamread C program included with Xillybus that let me read from the FIFOs. I edited it so it could write to a file so I'm saving all the data in binary mode then I open it using a hex editor. As long as it's running, the file being written increases its size but it's full of 0s, as if the XADC wasn't converting at all.

I'm not sure if you're familiar with Xillybus, if you are you might point out what I am doing wrong? If you're not, I'd appreciate it if you told me how to get some test readings from XADC as the one you @jpeyron or @Sam Bergami showed in your screenshots. What program are you running? The one that outputs the temperature and the Vaux8 voltage.

I tried running @jpeyron .bit (included in the zip you uploaded) but I wasn't successful on getting it working. I got a few erros when I opened it in Vivado and couldn't properly load the .bit file in the Zedboard.

Thank you!

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Hi @gutielo,

For my project and the screen shots I followed(for the most part) the lab 3 here with Vivado/SDK 2016.4. The progam that showed the data was tera term.  Unfortunately I do not have any experience with Xillybus. Hopefully others in the forum will have some input for you. 

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Hi @gutielo,

Looking at the reference manual for the xadc here. On page 29 it discusses that the xadc's max conversion rate is 1 MSPS which implies the max ADCCLK frequency is 26 MHZ. I have attached a screen shot of the xadc wizard with the project I have set up.  The axi clock is running at 100 MHz but the IP core is only sampling at 1 MSPS. You can look at my working project above in Vivado 2016.4.

cheers,

Jon

zedboard_xadc_4.jpg

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thanks @jpeyron  i have a signal generator from which iam going to generate a 1KHZ sine wave signal attached below and wanted to feed  input to vaux0 pin(zedboard xadc header)  since i have 2 knobs in signal generator positive voltage knob  and ground  knob  so i thought to connect vauxp to 0.5v and vauxn to ground knob by using strip wires.one end of the strip wire connected to xadc  header and the other end of the strip wire connected to the signal generator knobs(wires can be rolled in that knob).so could i proceed in this way  as i dont have AMS evaluation card.

if yes here the question arises  since i have only two knobs +Voltage knob and ground knob which i wanted  to give to  vauxp and vauxn then how about AGND and Vref pin do i need to connect it or can it be left open? please do let me know sir

signal-generator-500x500.jpg

xadc instantiation.PNG

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Hi, Guys,

 

I had the same application runing on a ARTY-Z7-20 board. I would like to confirm that the output we get is only from 0V to 0.999V (It clips outside that range. I thought we would get readings from 0V up to 2.5V.

If it is only up to 1V, why is there a integer portion of the reading and a decimal portion of the reading in the SDK software ?

Thanks

Antonio

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Hi @Antonio Fasano,

The 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide describes the input range of 0v to 1v in unipolar mode and -.5v to .5v for bipolar mode for the XADC. You would need to reach out to Xilinx support about their SDK code having an integer and decimal portion.

thank you,

Jon

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Thank you @jpeyron

Can you be more specific with the pins. We tried making the connections that you suggested above and received readings of 0 volts for all. We think this is because we aren't connected to the proper pins. Below we are attaching a picture of our xadc header pin connections.

Blue - Connected to Ground (AGND)

Yellow - Connected to Ground (AGND)

Green - Connected to Voltage : 0.5V (Vaux8N)

White - Connected to Voltage : 0.7V (Vaux8P)

Grey - Connected to Ground (AGND)

Black - Connected to Ground (Vref)

IMG_4862(1).JPG

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Hi @Sam Bergami,

I did not see vp/vn in the xdc but vp is on pin L11 and vn in on M12 as shown on the schematic page 8 and page 2 here. Unfortunately i have not worked with the xadc on the zedboard. I have attached the project I have been trying to get to work based on the lab 3 I linked from your other forum thread. I will try to get this working tomorrow and will reach out to my co-workers to see if they have any other input. Also another place you could reach out for assistance for the zedboard is here. 

cheers,

Jon 

zedboard_xadc.zip

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