Compare a string with data stored in FPGA

[mihai5]

Hi,

    I want to implement in Vivado a hardware implementation which will program the FPGA to create 4 register of 128 bit data and 4 comparators. First entries of the comparators will be linked to these 4 registers and the other entries will be linked to a single 128 bit register received from PS.

I attached i picture (A picture is worth a thousand words).
Please guide me with an exemple, start point in solving this issue.

[artvvb]

@mihai5

You may want to review this tutorial on how to create a custom AXI IP core, as this is Vivado's preferred way of communicating between PS and PL. The actual string comparison is fairly straightforward to do in verilog/vhdl, as ascii bytes are just bytes. You will need to decide early whether you need the 128 bit data to be compared against to be able to be changed by PS, as this may change how you encode your AXI slave registers. I suppose the question is really: where are the data registers are being set from?

Also, I love the picture, thank you.

Hope this helps,

Arthur

[mihai5]

@artvvb

             Thank you for your very quick answer. For now, I want that these 4 registers to be initialized at FPGA initialization. After this stage, I want to use a FIFO mechanism because these FPGA register will store temporally data. Finally i want to know if a string (picture - B entry from the comparator) is within a vector of strings (picture - A entry).

[artvvb]

This makes sense and should be achievable,

My recommendation would be to get PS-PL communication going first - try to display an ASCII character from PS on the LEDs of your board. The tutorial I linked above should help with with.

You can find a fairly hack-ey verilog example that handle strings in the top file for the Genesys2 OLED Demo. This demo is more focused on transmitting bytes in order than with managing entire strings at once. But the code is decently readable (I hope).

Hope this helps,

Arthur

[mihai5]

@artvvb

I'm trying to figure out how to get back to PS the data processed in FPGA. In the tutorial that you pointed to me, data received in FPGA ends up there by pulsing the leds. I want to get back that data and print out in user program.

[artvvb]

@mihai5

If you are in Vivado 2016.1 or later, there is a fast workaround you can try. It's very much a hack, but you can connect inputs and outputs of a module in your block design to AXI GPIO controllers configured as all input or all output. This is more a way of quickly prototyping a design which you would be creating a full AXI IP for later, but does work.

First, add your module written in HDL to the block design by right clicking and selecting "Add Module". Then add some number of AXI GPIO IP cores to your design, you can then customize their widths and input / output directions appropriately. After this, expand the GPIO Interface of each IP by clicking the plus button on the interface port in the block design screen. You can then do a click-drag connect to connect your module's inputs and outputs to the GPIO controllers.

Picture attached shows an example of the results of this.

As for actually creating a proper AXI interface, sending data back to PS is accomplished by setting the slave registers (slv_reg_#) of your choice, possibly changing other places that they are being set, it's been a little while since I created a full AXI core.

Hope this helps,

Arthur

[mihai5]

@artvvb

Thank you for your time and also for your picture. Can you please upload the test IP, or the entire project to use it as an exemple?

First i want to calculate the sum of two numbers in PL and print it out in user program. I can not find a trivial tutorial to make this trivial thing entirly.

I saw in this tutorial that data sent from PS to PL is written to a specific address generated for my IP, which can be seen in "Vivado - Address Editor". Writing in user program with Xil_Out32() function to this address produce the filling up of registers slv_reg# inside the IP. I tried to put my data that i want back in PS into slv_reg3 for exemple, and then to access that value from user program throught Xil_In32() function but I get the following error ("slv_reg3 has multiple drivers").

I saw that for comunication PL-PS from user program, i need to user Xil_Out32() and Xil_In32(). 

Thank you,

Mihai

[Notarobot]

Dear @mihai5

By asking for giving you full IP for your school project you put Digilent staff in a diificult position because it would be unethical to supply you with the complete solution. You had been given sufficient information to finish it. It does require minimal effort to get it working.

Please understand this.

Good luck!

[mihai5]

@Notarobot @artvvb

Sorry about this. I just wanted to know how the output of test IP is manipulated inside. I made a simple assign to the ouput wire "result"(see pic3-ip.png) but always give me in the user program value 0 instead value 8 (see pic2-sdk.png ).

What i have to change to give the right value (8) in user program ?

Sorry for this wrong situation.

[artvvb]

The values that are read back over AXI are modified by changing what the "reg_data_out" register is set to. There should be a case statement in the IP wrapper that looks a little like this:

2'h0   : reg_data_out <= slv_reg0;
2'h1   : reg_data_out <= slv_reg1;
2'h2   : reg_data_out <= slv_reg2;
2'h3   : reg_data_out <= slv_reg3;

This case statement needs to be modified so that on the appropriate read address, reg_data_out is set to your result.

Hope this helps,

Arthur

[artvvb]

@mihai5

It also looks to me like the result port in your block design is only 1 bit wide? This seems very likely to be the cause of getting a 0 instead of 8.

Hope this helps,

Arthur

[mihai5]

@artvvb

Thank you Arthur. You helped me a lot with your responses. Now i try to figure out how to use a parallelized mechanism. I created two blocks that function as two comparators. There are 2 different address created for that blocks(0x43C10000 and 0x43c20000 - each has 64k). In sdk, I need to write secvential in that two addresses, resulting a non parallelized mannerr. How can I achive a parallelized manner send data to that two comparators?

[jpeyron]

Hi @mihai5,

Could you post a screen shot of your current block design as well as your SDK code. 

thank you,

Jon

[mihai5]

Hi @jpeyron

   Maybe my last question is ambigous and a newbie one, but i want to know how use the parallelized mechanism in this scenario. I want to use these two comparators in parallel, in the sense that i want to sent data to a specific address, and somehow from this address can both read the same data and compare to their containing register value(please see also the initial picture).

Thank you,

Mihai

[D@n]

@mihai5,

What you *want* to do is to write to a peripheral that you can just *DUMP* data to as fast as the CPU can write it, while having the PL process it.  The processing you'll want to do is going to look like a giant state machine.  Indeed, such statemachines often end up so large they need SDRAM memory access.  For example, to compare two strings, you'll want the CPU to dump one string to the PL, and you'll want the PL to already know the second string--perhaps from SDRAM, perhaps from block RAM.

One difficult part you may not have thought about is ... what happens if you are trying to match to a string like: "HHELLO HH".  How will you synchronize your pattern matcher to the beginning of this string?  When you receive an H, is that the beginning of the pattern, or just the middle of the pattern?  Again, after you receive "HH", what state do you want to be in?  Suppose you receive the string "HHELLO HHELLO HHELLO" ... how many patterns do you wish to declare matches to?  The pattern exists within there twice, but the two patterns overlap.

If you can read data from the CPU, that's the first part.  You should be able to do just about all of the rest in your PL.

Dan