Xilinx CoolRunner II CPLD

[hsingh]

Hi,

I want to purchase Xilinx CoolRunner II CPLD (part no. 410-047-C2P-KIT). My Question is as follows.

1. Can I take the chip out from the board and re insert it again? will it keep the program stored or not.

2. I have a verilog program and Xilinx ISE software. Can I put verilog program on the Xilinx CoolRunner II CPLD? What are the accessories if needed. Please advice.

Regards,

Harpreet Singh

[davep238]

Hi,

I want to purchase Xilinx CoolRunner II CPLD (part no. 410-047-C2P-KIT). My Question is as follows.

1. Can I take the chip out from the board and re insert it again? will it keep the program stored or not.

2. I have a verilog program and Xilinx ISE software. Can I put verilog program on the Xilinx CoolRunner II CPLD? What are the accessories if needed. Please advice.

Regards,

Harpreet Singh

1) ​The board was made so that the CPLD could be used without removing the CPLD chip.  You could desolder the chip, use it, and re-solder it, but I doubt you could do that very often without either damaging the board or the chip.  2) All you need to program the chip is ISE and a download cable.  The Digilent JTAG HS2 cable should work for your application. If ISE does not work with this cable, then you will have to use Digilent's free Adept software. 3) Run ISE to make sure that your design will fit into the CoolRunner II part (XC2C64).  If it does not fit, you will have to simplify your design or use a larger part.

HTH

-Dave Pollum

[kampianakis]

Same questions here.

Also, what is the memory of the  Xilinx CoolRunner II CPLD if any and what is the fastest clock that I can drive it with?

Thanks!

Lefteris

 

[JColvin]

Hi,

Also, what is the memory of the  Xilinx CoolRunner II CPLD if any and what is the fastest clock that I can drive it with?

You can find the maximum clock frequencies on page 6 of it's datasheet from Xilinx. I'm not seeing that it has any on-board memory, although I could be wrong about that.

Thanks,
JColvin

[davep238]

Hi,

You can find the maximum clock frequencies on page 6 of it's datasheet from Xilinx. I'm not seeing that it has any on-board memory, although I could be wrong about that.

Thanks,
JColvin

​The CPLD is basically a bunch of gates and flip-flops.  It is not a memory chip.  The XC2C64 CPLD has a total of 64 flip-flops.  Each flip-flop can hold 1 bit.  Each flip-flop is contained in a Macro-Cell along with some logic.  There are also lots of other logic gates on the chip.  You can fit simple state machines and decoders, etc. in this chip.  Have you tried running ISE, especially the CPLD fitter, to see if your design fits into the CPLD?  The ISE tool also shows the maximum frequency that your design will run.  This may be less than the max frequency of the chip itself.

-Dave Pollum