External Pins to AXI4 IP not routed

[Farid]

I developed an IXI4 on Zedboard with 3 external input port, and I assigned there PIN mapping on my XDC file. However, after I implemented the design I found out that these input nets were not created. I verified that these inputs I assigned are correct.

Also if I run only the PL without AXI4, the nets are created and everything works fine. Could any one suggested why the pins mapping is affected once I added the PS and AXI4 to my design?

[elodg]

First, open the synthesized design netlist in the IP project and see if anything got optimized due to bad HDL. Then, do the same in the project that instantiates your IP and ties the AXI bus to a master. Watch for warnings related to nonexistent objects, inputs hard-wired to constants or unused signals.