Using HLS OpenCV in Arty hdmi_in reference design

[RajatRao]

Hello,

I have a Arty-Z7-20 board and got the hdmi_in demo working on it.

I need to process the incoming hdmi stream and I found that doing it as an application on Zynq is too slow because pixel accesses are required.

I would like to use the OpenCV functions in HLS to do this. I wrote the following program in HLS -

#include <hls_video.h>

void video_resize(hls::stream< ap_axiu<24,1,1,1> > &video_in, hls::stream< ap_axiu<24,1,1,1> > &video_out)
{
#pragma HLS INTERFACE axis port=video_in bundle=INPUT_STREAM
#pragma HLS INTERFACE axis port=video_out bundle=OUTPUT_STREAM

 hls::Mat<1080, 1920, HLS_8UC3> src;
 hls::Mat<1080, 1920, HLS_8UC3> dst;
#pragma HLS dataflow
 hls::AXIvideo2Mat(video_in, src);
 hls::Scale(src, dst, 2.0, 0.0);        //Simple processing
 hls::Mat2AXIvideo(dst, video_out);
}

 

My questions are -

1) Where in the demo block design should I connect this?

     (a) Between the video-to-axi4-stream ip and the axi-vdma ip

     (b) Add 1 more axi-vdma IP with both read and write channels and connect to it

     (c) Some better alternative?

 

2) In HLS, this design was synthesized with a clock constraint of 6.7 ns, so it meets the HDMI clock constraint of 148.5 MHz. However, in IP Integrator, a default value of 100 MHz is taken and I am unable to change this. What is the solution?

 

3) Is there any Digilent reference design/demo that already has HLS OpenCV IP integrated into the block design?

     Xilinx provides XAPP1167, but this only compiles on 2014.4 version which I don't have. I don't know how to upgrade the design to the current version.

 

I might be asking too much, but any help is appreciated.

 

Thanks,

Rajat Rao

[jpeyron]

Hi @RajatRao,

I have reached out to a more experienced engineer to look at your forum question.

cheers,

Jon

[RajatRao]

I have made some progress since I posted the question.

1,2) The clock problem was due to connecting the axilite interface and the video streaming interface to different clock domains. Once I connected both to clk1 of the reference design, it works smoothly. The HLS IP was inserted between the video streaming IP and the AXI VDMA IP. I would still like to have an educated opinion on the best way to do video processing.

3) I would still appreciate if someone could tell me how to upgrade the design without the relevant Vivado version.

A huge thank you to Digilent for providing such an excellent demo (hdmi_in for Arty Z7). It really helped me learn a lot.

[elodg]

The easiest way is getting that version, running the scripts to generate the hardware project and then opening it in your new version, where an upgrade will be performed.

The hard route is going into build_bd_design.tcl and manually editing it to deactivate the version warning and modify all IP versions to their current version in "create_bd_cell" commands. Then trial-and-error until the project gets generated without errors. Depending on the IP changelogs there might be interface differences, but those are rare.