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smarano

Program CMod A7 35T without Vivado

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Hi,

I have a question, there is a way to programm my Cmod A7 without Vivado->Hardware Manager? 
I got some issues with Vivado, sometime crash. 
Another question is, there is a way to separate programming phases?
At moment i have a download.bit, firmware.srec and data.txt, with hardware manager i have fused them in firmware.mcs and have flashed it in my SPI Flash. 
There is a way to program my flash only with download.bit and firmware.srec and later with data without overriding the other memory banks? 
Kind Regards

Stefano

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Hello, 

Unfortunately the XC7A35T FPGA is not supported by ISE tools, so you should use Vivado. Can you try using a different Vivado version ?

Good luck.

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@smarano,

Is there a way?  Yes.  Having programmed my Arty board via Vivado once, I can now program and adjust the SPI flash on it as I see fit.  This includes overwriting the configuration, if I wish, as well as writing an alternate configuration and then configuring from that.

Consider the scenario: you don't want to program from Vivado at all.  So, you load an initial configuration onto your device.  You then want to try out a new configuration.  Write that new configuration to a designated area in flash (you get to pick--just make sure things don't overlap), and then tell the FPGA via the ICAPE2 interface to go and configure itself from that alternate configuration area.

Want to load the other portions of flash with information?  Sure!  Just say where.

The tools I use for doing this include:

  • A QSPI flash controller.  The Basys3 has one type of QSPI flash, the other boards I've worked with have another.  There are controllers in this repository for handling both.
  • A wishbone to ICAPE2 converter, so I can control the ICAPE2 port via a wishbone bus--like all my other peripherals.  This also gets around the confusing spec's of how to control the ICAPE2 port, by encoding once and for all how to do it against an open standard.  The documentation within the repo should be enough to tell you how to restart your FPGA from any flash location.  It'll also point you to Xilinx's docs.
  • A debug access port that controls an on-board wishbone master.  You can find a copy of this port in both the ZBasic as well as the OpenArty repositories under the name wbubus.v for the Verilog portion, and ttybus.v for the corresponding C++ necessary to interact with it.
  • The OpenArty repository even has a wbprogram command  that will reprogram your flash.  It depends upon having a flash controller on board (link above), and the software to support it, but all of these are available within the repo.  And, yes, it understands both bit and bin files.
  • There's also a zipload facility that I'm using to load ELF files onto the flash.
  • And ... if that's not enough, both OpenArty and ZBasic have a Verilator based simulation you can use, together with a flash simulator, that will allow you to test whether your flash solution works or not.

Let me come back to your questions:

  1. Is it possible to separate the programming/configuration phases?  Yes.  I often build my designs so that the onboard ZipCPU starts in a halted state/configuration.  I can then load the ELF file program either directly into memory or directly into the flash after loading the configuration.  Once loaded, I can then start the ZipCPU.
  2. The trick is that you need to maintain a configuration that the design will start into automatically, from which you can then do your work.  If you lose this startup design, you'll have to go back to Vivado to put a new one onboard.  (Upgrading the startup design is easy without Vivado--unless things go wrong ... ;))
  3. Can you program parts and pieces of your flash at a time?  Yes, well, sort of.  If you want to turn a zero to a one you'll need to ERASE an entire section of your flash (4kB IIRC).  If you want to then turn a one to a zero, you'll need to program the flash.  Programming can affect as little as one byte if you would like.  The trick is the ERASE part.  If you wanted, there's nothing keeping you from reading out the second as it is, ERASEing the whole section, and then programming it back to what it was ... with the changes you've made.  This all makes sense from a PC controlling things.

Bottom line: it's all doable.  All my work, though, has been with the ZipCPU.  Although I've never done any of this using microblaze, with a little bit of creativity you should find that most all of this remains doable as well.  I mean, they both use ELF files, right? :)

Dan

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Hi D@n,
thanks for your reply. I have seen your solution but i have founded another solution, more easy. With Vivado i have generated a firm.mcs without data, so it's generic and i can flash all my fpga only once. Then i have generated another .mcs file only with data, so if i need to refresh o change my data, i need to change only data.mcs. 
Yes, i don't like Vivado, i would another Software like Impact to flash my fpga. But there seems to be no others. 

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