I'm trying to run the XAPP 1079 on Zybo. As the profile is not originally made for this specific board, I had to make some changes. I follow all the insructions for the Vivado and the SDK, but in the end after the board boots from the microSD card I don't see anything in the terminal. I was wondering first if the changes that I made are correct and if anymore are needed. One specific issue I am having is that while creating an instance of the Zynq7 processor, it uses the configuration preset for the ZC702 board. Can/Should I change that?
Below are the tcl scripts that i have modified.
Spoiler
################################################################
# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2017.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl
# If you do not already have a project created,
# you can create a project using the following command:
# create_project project_1 myproj -part xc7z010clg400-1
# set_property BOARD_PART digilentinc.com:zybo:part0:1.0 [current_project]
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
# CHANGE DESIGN NAME HERE
set design_name design_1
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
puts "INFO: Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
puts "INFO: Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
puts $errMsg
return $nRet
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
# Create ports
# Create instance: ila_0, and set properties
set ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_0 ]
set_property -dict [ list CONFIG.C_ENABLE_ILA_AXI_MON {false} CONFIG.C_MONITOR_TYPE {Native} CONFIG.C_NUM_OF_PROBES {4} ] $ila_0
# Create instance: irq_gen_0, and set properties
set irq_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:irq_gen:1.1 irq_gen_0 ]
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list CONFIG.PCW_CORE1_IRQ_INTR {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.preset {ZC702} ] $processing_system7_0
# Create instance: processing_system7_0_axi_periph, and set properties
set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ]
set_property -dict [ list CONFIG.NUM_MI {1} ] $processing_system7_0_axi_periph
# Create instance: rst_processing_system7_0_100M, and set properties
set rst_processing_system7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_processing_system7_0_100M ]
# Create instance: vio_0, and set properties
set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ]
set_property -dict [ list CONFIG.C_NUM_PROBE_IN {0} ] $vio_0
# Create interface connections
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins irq_gen_0/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI]
# Create port connections
connect_bd_net -net irq_gen_0_IRQ [get_bd_pins ila_0/probe2] [get_bd_pins irq_gen_0/IRQ] [get_bd_pins processing_system7_0/Core1_nIRQ]
connect_bd_net -net irq_gen_0_slv_reg [get_bd_pins ila_0/probe1] [get_bd_pins irq_gen_0/slv_reg]
connect_bd_net -net irq_gen_0_vio_rise_edge [get_bd_pins ila_0/probe0] [get_bd_pins irq_gen_0/vio_rise_edge]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins ila_0/clk] [get_bd_pins irq_gen_0/S_AXI_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_100M/ext_reset_in]
connect_bd_net -net rst_processing_system7_0_100M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins rst_processing_system7_0_100M/interconnect_aresetn]
connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins irq_gen_0/S_AXI_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins ila_0/probe3] [get_bd_pins irq_gen_0/VIO_IRQ_TICK] [get_bd_pins vio_0/probe_out0]
# Create address segments
create_bd_addr_seg -range 0x10000 -offset 0x78600000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs irq_gen_0/S_AXI/reg0] SEG_irq_gen_0_reg0
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
Spoiler
# Create project
set proj_name project_1
create_project -force $proj_name ./$proj_name
# Set project properties
set obj [get_projects $proj_name]
set_property "part" "xc7z010clg400-1" $obj
set_property "target_language" "Verilog" $obj
set_property board_part digilentinc.com:zybo:part0:1.0 $obj
# Set the directory path for the new project
set proj_dir [get_property directory $obj]
set_property ip_repo_paths $proj_dir/../../src/my_ip [current_fileset]
update_ip_catalog
#create BD
source $proj_dir/../../src/scripts/create_bd_701.tcl
validate_bd_design
save_bd_design
#Create top wrapper file
make_wrapper -files [get_files $proj_dir/$proj_name.srcs/sources_1/bd/design_1/design_1.bd] -top
import_files -force -norecurse $proj_dir/$proj_name.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
#implement the design and create bit file
launch_runs impl_1 -to_step write_bitstream
wait_on_run -timeout 60 impl_1
#Export design to SDK
file mkdir $proj_dir/$proj_name.sdk
file copy -force $proj_dir/$proj_name.runs/impl_1/design_1_wrapper.sysdef $proj_dir/$proj_name.sdk/design_1_wrapper.hdf
launch_sdk -workspace $proj_dir/$proj_name.sdk -hwspec $proj_dir/$proj_name.sdk/design_1_wrapper.hdf
I have tried running the profile both on the 2017.1 and the 2015.4 version of Vivado. It is possible that it has something to do with the standalone bsp. I have tried running a simple hello world from a single core of the ARM A9 and it runs just fine. But when I try running a simple hello world application with both the cores (essentially changing the SDK part of the XAPP), I still see nothing on the terminal.
Question
vic
Hi,
I'm trying to run the XAPP 1079 on Zybo. As the profile is not originally made for this specific board, I had to make some changes. I follow all the insructions for the Vivado and the SDK, but in the end after the board boots from the microSD card I don't see anything in the terminal. I was wondering first if the changes that I made are correct and if anymore are needed. One specific issue I am having is that while creating an instance of the Zynq7 processor, it uses the configuration preset for the ZC702 board. Can/Should I change that?
Below are the tcl scripts that i have modified.
# Create project set proj_name project_1 create_project -force $proj_name ./$proj_name # Set project properties set obj [get_projects $proj_name] set_property "part" "xc7z010clg400-1" $obj set_property "target_language" "Verilog" $obj set_property board_part digilentinc.com:zybo:part0:1.0 $obj # Set the directory path for the new project set proj_dir [get_property directory $obj] set_property ip_repo_paths $proj_dir/../../src/my_ip [current_fileset] update_ip_catalog #create BD source $proj_dir/../../src/scripts/create_bd_701.tcl validate_bd_design save_bd_design #Create top wrapper file make_wrapper -files [get_files $proj_dir/$proj_name.srcs/sources_1/bd/design_1/design_1.bd] -top import_files -force -norecurse $proj_dir/$proj_name.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v #implement the design and create bit file launch_runs impl_1 -to_step write_bitstream wait_on_run -timeout 60 impl_1 #Export design to SDK file mkdir $proj_dir/$proj_name.sdk file copy -force $proj_dir/$proj_name.runs/impl_1/design_1_wrapper.sysdef $proj_dir/$proj_name.sdk/design_1_wrapper.hdf launch_sdk -workspace $proj_dir/$proj_name.sdk -hwspec $proj_dir/$proj_name.sdk/design_1_wrapper.hdfI have tried running the profile both on the 2017.1 and the 2015.4 version of Vivado. It is possible that it has something to do with the standalone bsp. I have tried running a simple hello world from a single core of the ARM A9 and it runs just fine. But when I try running a simple hello world application with both the cores (essentially changing the SDK part of the XAPP), I still see nothing on the terminal.
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