Hi, I need your help please, actually I am work in an arduino communication with FPGA (Basys3), but i have a problem with the implementation, can you help me?
VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SPI_rx3_top is
Port ( SCK : in STD_LOGIC; -- SPI input clock
DATA : in STD_LOGIC; -- SPI serial data input
CS : in STD_LOGIC; -- chip select input (active low)
led : out STD_LOGIC_VECTOR (7 downto 0) := X"FF");
end SPI_rx3_top;
architecture Behavioral of SPI_rx3_top is
signal dat_reg : STD_LOGIC_VECTOR (7 downto 0);
begin
process (SCK)
begin
if (SCK'event and SCK = '1') then -- rising edge of SCK
if (CS = '0') then -- SPI CS must be selected
-- shift serial data into dat_reg on each rising edge
-- of SCK, MSB first
dat_reg <= dat_reg(6 downto 0) & DATA;
end if;
end if;
end process;
process (CS)
begin
if (CS'event and CS = '1') then
-- update LEDs with new data on rising edge of CS
led <= not dat_reg;
end if;
end process;
end Behavioral;
[Place 30-876] Port 'SCK' is assigned to PACKAGE_PIN 'B15' which can only be used as the N side of a differential clock input. Please use the following constraint(s) to pass this DRC check: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SCK_IBUF}]
[Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
Question
sanrod
Hi, I need your help please, actually I am work in an arduino communication with FPGA (Basys3), but i have a problem with the implementation, can you help me?
VHDL:
XDC:
## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {CS}] set_property IOSTANDARD LVCMOS33 [get_ports {CS}] ##Sch name = JB2 set_property PACKAGE_PIN A16 [get_ports {DATA}] set_property IOSTANDARD LVCMOS33 [get_ports {DATA}] ##Sch name = JB3 set_property PACKAGE_PIN B15 [get_ports {SCK}] set_property IOSTANDARD LVCMOS33 [get_ports {SCK}]
Warnings:
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