always @(posedge btnC)
if (0) begin
led <= 5'b0;
end else if(1) begin
led = led + 1;
end
endmodule
If I change the always trigger condition to posedge clk it works fine (The leds turn on and off so fast I barely see anything but with an oscilloscope it can be seen),
but when I want to trigger the counter with the C button I get these errors when generating the bitstream:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnC_IBUF] > btnC_IBUF_inst (IBUF.O) is locked to IOB_X0Y13 and btnC_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
[Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
I tried including/excluding clock constraints and the clock from the modules parameter list, all possible combinations, nothing helped (the errors change).
Question
rafauy
Hi Everyone,
I tried some tutorials and the forum but couldn't find much help with this. Im using a Basys3 board with Vivado ISE webpack.
I want to make a 5 bit binary counter that increments every time C button is pressed and the value is displayed in 5 leds.
I wrote the following code:
module Adder32(input wire btnC, input wire clk, output reg [4:0] led);
always @(posedge btnC)
if (0) begin
led <= 5'b0;
end else if(1) begin
led = led + 1;
end
endmodule
If I change the always trigger condition to posedge clk it works fine (The leds turn on and off so fast I barely see anything but with an oscilloscope it can be seen),
but when I want to trigger the counter with the C button I get these errors when generating the bitstream:
I tried including/excluding clock constraints and the clock from the modules parameter list, all possible combinations, nothing helped (the errors change).
My constraints are:
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
Thanks!
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