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Vivado Constraints file .xdc



I am currently working on a project in Vivado 2017 using the external mux. I have more of a general question concerning the constraints file (.xdc). How does one go about creating their own xdc file? Normally, do you start with the full zedboard constraints file and comment things in yourself or can Vivado create one for you? Also is there a place I can look that explains the complete constraints file for the Zynq 7000 and when to use them?



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Hi Sam,

May I suggest to elaborate what is it you want to make. It will help others to help you.

Based on my knowledge there are at least two type of constrains, one describing physical interface that is binding of the internal logic to the chip pins and the second is about timing constraints. I assume that you are asking about the first one. I am not aware of any possibility to generate such constraints automatically because it is highly dependent on PCB routing which is different for every board. Typically this is decided by the board designer during optimization process.

For every commercial board manufacturers include .xdc file describing all connections to installed ports: Pmods, RS232, etc. Since you are using Zedboard you can uncomment statements in .xdc file and rewire some of default connections, for example if you want to use XADC for reading expernal voltages.

Xilinx DocNav is the place to learn about constraints. In my experience it is not the easiest but this is information from the first hands without distortions.

Good luck!


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@Sam Bergami,

What I personally dislike about the process of starting with a master XDC file and commenting out the lines you want to keep, is ... what happens when you want to "try out" a different configuration?  You've got to go back and edit the XDC file to be ... something else just for that configuration.

I find it annoying.

So my thought is that you should be able to specify which components within a design that you wish to include, and then have only the wires associated with those components be adjusted.  I have a preliminary capability of that working in the autofpga project I'm working on.  In that project, you can list the components you want to incorporate in your design, and the autofpga program will assign wishbone addresses to those components, build the interconnect, assign interrupts, build a high level main module, a top level module, and even a main test bench module.  While in many ways it remains a work in progress, you can find a working example of what it does in the ZBasic project.

I'm currently working on teaching the application how to handle bus'es of different types (AXI SDRAM vs Wishbone B4 vs B3), different widths, and different clock rates.  Those are capabilities I'm finding I need for dealing with video--but that's neither here nor there.


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