External single ended clock by FMC connector in Genesys2

[rappysaha]

Hello everyone,

I need suggestion about following topic:

1) I want to use an external oscillator 54 MHZ. And I want to take input this clock by FMC connector HA/LA pair (3.3 V) of genesys2 board. Is it will be ok?

2) The fixed oscillator 200 MHZ in Genesys2 is differential. I am producing my master clock for my design by MMCM. How can I have the minimum jitter? 

Any suggestion will be very helpful.

Thank you

Rappy Saha

 

 

 

 

[jpeyron]

Hi @rappysaha,

For the FMC you should be using the pins labeled FMC_CLK0 or FMC_CLK1... these pins were designed for clock input from the mezzanine to the board. I have reached out to my co-workers to see if they have any input on your second question. Have you looked into the clocking wizard?

cheers,

Jon 

[rappysaha]

Hi @jpeyron,

Thank you for your information. 

But, I have already fixed the clock pin H38(LA32_N) in my mezzanine board. I don't know how it will affect the clock. Any comment will be helpful.

And I am also using the clock wizard IP and I am using  "minimized jitter" option in Clock wizard IP. Is it the only way?

Thank you

Rappy Saha 

[D@n]

@rappysaha,

The MMCM will increase the jitter in your clock, a PLL on the other hand will reduce it.

While the clocking wizard IP is fine for use, .... I've never used it.  You may find it valuable, but you don't have to find yourself constrained by it.

Dan

[rappysaha]

Hi @D@n,

Thank you Dan. I will try to use the PLL feature. But, why PLL should have less jitter than MMCM? It will be helpful to me if I know the reason.

I will be grateful to you.

Rappy saha

[D@n]

@rappysaha,

Looks like my info was out of date.  Here's a discussion of the differences between the two, suggesting that the PLL is actually a subset of the MMCM, so ... I'm not certain any more.

Dan

[jpeyron]

 

Hi @rappysaha,

Depending on what you are doing with the signal on H38(LA32_N) you might have issues with the logic in the FPGA. If that becomes the case then I would suggest to use any of the pins that connect to SRCC or MRCC on the FPGA. I am not familiar with any other way to reduce the jitter. I will ask my co-workers to look at this and see if they have anything else they can input

thank you,

Jon