I'm trying to learn how to use it properly but sometimes it's just hopeless.. My design works in hardware but not in the simulator. I get "undefined" as always on my output, which is obviously a lie, I feel violated.
Yesterday I posted a design on a signal synchronizer or stabilizer but I suspect it might be susceptible to metastability so I decided to redesign it today using more flipflops instead of a sneaky xnor gate on an enable pin.
I want the thing to ignore signal changes that are shorter than two clock cycles. I made a state diagram:
A state transition table:
And the next state calculations (I suggest you just read the code, I've written it there too obviously but it's actually readable):
Here's the code for the actual module:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IO_sync_v2 is
Port ( clk, I : in STD_LOGIC;
Q, I_R, I_F : out STD_LOGIC);
end IO_sync_v2;
architecture Behavioral of IO_sync_v2 is
component D_flipflop is
Port ( clk, d : in STD_LOGIC;
q : out STD_LOGIC);
end component;
signal s0, s0p, s1, s1p, s2, s2p, q_pre, q_new : STD_LOGIC := '0';
begin
Delay_0: D_flipflop port map(clk => clk, d => s0p, q => s0);
Delay_1: D_flipflop port map(clk => clk, d => s1p, q => s1);
Delay_2: D_flipflop port map(clk => clk, d => s2p, q => s2);
Edge: D_flipflop port map(clk => clk, d => q_new, q => q_pre);
s2p <= (s2 and (s0 xnor I)) or (s1 and s0 and not I);
s1p <= I and (s1 or (s2 xor s0));
s0p <= (not s0 and (s2 or s1 or I)) or (s1 and I);
q_new <= (s2 and ((s0 xnor I) or I)) or (s1 and (s0 or I));
Q <= q_new;
I_R <= not q_pre and q_new;
I_F <= q_pre and not q_new;
end Behavioral;
The testbench:
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity IO_sync_v2_tb is
end;
architecture bench of IO_sync_v2_tb is
component IO_sync_v2
Port ( clk, I : in STD_LOGIC;
Q, I_R, I_F : out STD_LOGIC);
end component;
signal clk, I: STD_LOGIC;
signal Q, I_R, I_F: STD_LOGIC;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
begin
uut: IO_sync_v2 port map ( clk => clk,
I => I,
Q => Q,
I_R => I_R,
I_F => I_F );
stimulus: process
begin
-- Put initialisation code here
I <= '1';
wait for clock_period;
I <= '0';
wait for clock_period;
I <= '1';
wait for clock_period;
wait for clock_period;
wait for clock_period;
I <= '0';
wait for clock_period;
wait for clock_period;
wait for clock_period;
I <= '1';
wait for clock_period;
wait for clock_period;
I <= '0';
wait for clock_period;
I <= '1';
wait for clock_period;
I <= '0';
wait for clock_period;
wait for clock_period;
wait for clock_period;
I <= '1';
wait for clock_period;
wait for clock_period;
wait for clock_period;
I <= '0';
wait for clock_period;
wait for clock_period;
wait for clock_period;
I <= '1';
wait for clock_period;
wait for clock_period;
wait for clock_period;
I <= '0';
wait for clock_period;
wait for clock_period;
wait for clock_period;
-- Put test bench stimulus code here
stop_the_clock <= true;
wait;
end process;
clocking: process
begin
while not stop_the_clock loop
clk <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;
The simulation:
If this was true, my hardware would not work, but it does. What is the cause of this?
Question
Tickstart
I'm trying to learn how to use it properly but sometimes it's just hopeless.. My design works in hardware but not in the simulator. I get "undefined" as always on my output, which is obviously a lie, I feel violated.
Yesterday I posted a design on a signal synchronizer or stabilizer but I suspect it might be susceptible to metastability so I decided to redesign it today using more flipflops instead of a sneaky xnor gate on an enable pin.
I want the thing to ignore signal changes that are shorter than two clock cycles. I made a state diagram:
A state transition table:
And the next state calculations (I suggest you just read the code, I've written it there too obviously but it's actually readable):
Here's the code for the actual module:
The testbench:
The simulation:
If this was true, my hardware would not work, but it does. What is the cause of this?
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