FPGA Clock

[FlyMario]

I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question.

I have the FPGA connected to my Commodore 64 via Logic Level Converters.  And I am having lot of success.

I am reading 8 lines from the Keyboard port looking.  My verilog is simply looking for a matching value on those lines.  No problems at all.  But I am curious,  how is the logic managing to work when I have not really set up a clocking line.  Is the FPGA using main clock to trigger events to move on in the FPGA.  For instance,  if you have a blocking statement it would seem that in order to get past that block, there must be some clock checking the incoming value before the logic can continue.  Is this true?  Or am I missing something.

Is there a clock in the fpga that is pushing the logic along?

 

Flymario

 

[TrapperBob]

Flymario,

I am glad you are enjoying this activity!  I would ask the following questions:

1. Are you using a FPGA board that you have acquired or one that you created?

2. What does the schematic look like both for the board and how you have it hooked to your C64?

3. You said you are using Verilog and that it really does not matter. It does not matter except that without seeing the Verilog code we are unable to determine what your logic may be doing. Are you using combinatorial logic , synchronous logic or a little of both? Please show the code so we are not guessing!

[D@n]

@FlyMario,

Yeah, what @TrapperBob said.

FPGA's tend not to have integrated clocks--at least, I don't remember ever working with one where the clock was self sourced.  Instead, all of the FPGAs I've worked with (Spartan included) have required an external clock.  To know more about this clock to fully answer your question, I'd need to know what board you are working with.

If you want to know more about how to accomplish timing within an FPGA, given a system clock that everything runs off of, this basic verilog clocking blog article may be interesting to you.

Dan

[FlyMario]

Thanks a lot guys!  I will get back to you.

I guess I thought that when you have always block,  and you are putting in a blocking statement such as A = B;  that there must be some clock to check that B had a value to pass and unblock the statement.  There are so many contradicting statements on how this works.Blocking statements seem they would cause things to run in Series instead of Parallel.  Perhaps I am worrying about this too much.

Also, anyone have experience with C64 logic levels think that if I put a 20k resister from ground to the fpga pin and then a 10k resister from the pin to data line would protect the fpga from burning.  I use logic level converters but feels like a waste if I could just use a (voltage divider?) resister circuit for the 8 input lines I need.

Thanks FlyMario

[D@n]

@FlyMario,

Not at all.  The difference between blocking and non-blocking statements isn't a hardware difference, but a synthesizer difference.  The synthesizer allows you to use the two types when defining your logic, but once it gets to the hardware everything with a clock transitions only once on the clock.  Hence, all flip-flops are nonblocking <=.

Dan

[FlyMario]

Oh wow... thank you very much!  This answers the whole point of my long winded question!