Could You Help Me About Verilog?

[tirotry]

Hello to everyone,

I'm getting the hex data in the processor and I want to print to pmod ssd. I have an incorrect number. How do I decode 8 bits of hex data?

 

I am not good at English,sorry

[D@n]

@tirotry,

Did the example I posted you to help you at all?

Dan

[D@n]

@hamster,

Isn't that what all of these approaches will then create?  For example, the approach I just listed above ...

Dan

[hamster]

I know this sounds wrong, but....

A good way to convert 8-bit binary into Decimal Digits is most likely a 256 entry lookup table, giving an two 4-bit results. Yes, it will seem a lot of code, but it will implement very efficient, is fast, and will use very little power. You can also replace a lot of logic, if your conversion would otherwise involve constants (e.g. if you also need to calculate "out_val = k * in_val + c", like you would to convert degrees C into degrees F)

[D@n]

@tirotry,

Yeah ... there's a reason why that example used the divide within a C program to be run on a CPU, and not an FPGA program.  Divides can be ... hard on an FPGA.  They are doable, but they are hard.  In your case, you have an 8-bit input, so your synthesis tool should be able to generate a divide in just 4-LUTs and an 8-mux per bit ... it's doable.

Regarding buttons and switches ... which board do you have?  Were you able to create all 8-bits of the input using your buttons and switches?  Could you display every number that the display can produce?  If you can display a pair of hex digits without a problem, then ... the only problem you have is how to convert from binary to BCD, right?  Something like:

always @(posedge i_clk)
	if (i_data < 10)
    	o_data <= { 4'h0, i_data };
	else if (i_data < 20)
    	o_data <= { 4'h1, i_data[3:0] - 4'ha };
	else if (i_data < 30)
    	o_data <= { 4'h1, i_data[3:0] - 4'h4 };
... etc ...

One other question about your design ... what is setting S_AXI_WDATA?  and ... is it properly being set?  I can't tell, since it's not a part of your project.

Further, it looks like your are struggling to put too much logic into one component.  Take a step back.  Separate your logic between components.  This will help you reason about what is going on and produce better quality code.  Use one module to convert from a  7-bit binary value to an 8-bit BCD value.  Use another module to convert this into a list of LED's that need to be turned on.  Another module should have your counter in it, and should actually drive the various pins of the SSD.  By separating the components out like this, you'll find it easier to 1) write them, 2) maintain them, 3) know what is working and what isn't, etc.

Dan

[tirotry]

@artvvb Actually I found part of the code this website.  (line 47 ). I don't know clearly.
I saw on the SDK my data 0x001B.
 @D@n , I used SSD with buttons and switches it is working. Test was passed.
but  I did not project my problem is I am bad at verilog 

[D@n]

@artvvb,

Good catch!  I missed that one. 

@tirotry,

FPGA's can't really do "divides".  If you want to print in hex, set the second value to result[7:4].  Division is only required if you wish to write the result out in decimal,

Dan

[D@n]

@tirotry,

One problem common among students is that they connect several parts and pieces of their design together, and then get surprised when they don't work.  The component you posted, while it helps me understand what you are doing, is only part of your problem.  Can you separate this component from the other components in your design and test this component by itself?

The other problem you have is that (if I understand what you are doing properly), you are trying to set many LED's at once.  Don't.  LED's don't share power well.  Turn one LED light on at a time and then rotate between them.

I see you are already rotating between digits.  Slow down ... you are switching from one digit to the next too fast.  Try counter[16] instead of counter[9].

Having said all of this ... if you followed the methodology I gave you in my first reply to you (above), you might have a working SSD by now.    Go back and reread it.  It discusses the basic methodology of how to get an SSD port up and running.

Dan

 

[artvvb]

@tirotry

First, mixing blocking and non-blocking assignment ('=' and '<=') can make weird things happen.

Second, could you explain what line 47 is intended to do? That being:

value = (result / 10) << 4;

The value register is only 4 bits wide, and the following case statement only uses the lowest four bits of the value reg.

Thanks,

Arthur

[tirotry]

I see your code.. My code is this one and my S_AXI_WDATA is Hex I wan to see decimal on seven segment display

Thanks   @D@n

[tirotry]

Unfortunately no I did not solve.

[D@n]

@tirotry,

Does that mean your problem is solved?

Dan

[tirotry]

thanks a lot @D@n for every thing  

I am not good at English so somewhere I did not understand . but you are awesome becasue you want to solve every problem. I hope I can explain.

@artvvb
I use Pmod tmp3 and my pmod is writing data with hex. For example 0x01B. and I create seven segment IP and I want to see for example 27 on the two digit seven segment display.I hope I can explain.

thanks a lot.

[artvvb]

@tirotry

You may want to work through the learn module projects and design challenges up to this one.

Could you explain what you mean by hexadecimal and 8 bit binary here? What do you want the output to be?

Thanks,

Arthur

[D@n]

@tirotry,

Forgive me if I "refuse" to give you the answer ... but you might find this source file helpful. 

Dan

[tirotry]

thanks your answer @D@n  Actually I want to ask this : My input data hexadecimal but  I want to 8 bit binary 

[D@n]

@tirotry,

FPGA design work is one of those things that is done a little bit at a time if you wish to be successful.  Each little bit feeds on the next.

To get that SSD going, try this (in order):

1. Turn on one of the lights in the SSD.  Make it so your design does nothing but turning on one of the lights and that light only.
2. Build a new design, turning on a second light.  Make sure you understand which light is now being turned on.
3. Repeat, until you understand how to turn each of the lights on individually.
4. Create a module that will turn on a chosen light.  Adjust the switches on your board to select which light you wish to have chosen, and have that light turn on based upon the switch setting.
5. Now, build a state machine that walks through each of the lights, turning them on in order.  You can use this post as advice in how to build any of the timing information you need.  I'd recommend turning each light in your SSD on in turn, one at a time, perhaps rotating through them at one second each so you can see what is going on. 
6. As I recall, you don't want to turn any light on for less than 1ms, so when you are ready to go faster you may need to divide a 100MHz clock down 100k times.  (If you move faster than 1ms, you'll get more than one light turning on at a time.  I tried that once.  I didn't get the result I wanted .)

Think carefully about how you are going to go about your design process.  You don't want to end up in what I call FPGA Hell: that state where you cannot tell why the FPGA is (or isn't) doing what you want.  FPGA's are not like software.  It can be very difficult to get access to your internal variables.  I recommend when you get to step 4 above that you start simulating your design before going any farther.  (I use Verilator for my simulations, others use ... other simulators).

Dan