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Clarissa

Can't configure UART ports on NexysVideo board

Question

In my project, I need to use the UART ports on the NexysVideo board to transmit signals to a Raspberry.

I defined 2 signals Rx_raspi as an in std_logic and Tx_raspi as an out std_logic, and in the XDC file, they are defined as:

set_property -dict { PACKAGE_PIN AA19  IOSTANDARD LVCMOS33 } [get_ports  Rx_raspi ]; 
set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports  Tx_raspi ];

while implementing, errors show that no ports matched.

[Vivado 12-584] No ports matched 'Tx_raspi'. 
[Vivado 12-584] No ports matched 'Rx_raspi'. 
[Common 17-55] 'set_property' expects at least one object. 
[Common 17-55] 'set_property' expects at least one object. 

What was wrong?

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It looks like the name in the constraint doesn't match with the name in the module. Can you take out get_ports and synthesize the design? 

 

Edit: sorry I guess I was not awake in the morning. You may need {} instead of getting rid of get_ports. I guess someone else is helping you. 

Edited by Alex

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@Clarissa,

When I try getting a serial port up and running these days, I've started with the demo serial port files from this distro.  Specifically, the files in the bench/cpp directory provide an example hello world, echo, longer serial port dump, and a line read/dump facility.  They work very well for making sure you have your basic logic set up properly.  They don't work nearly as well if you don't have your XDC file set up properly, but you may find them to be a valuable next step.

Dan

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Hi @Clarissa,

Could you attach your wrapper file. Also try this as the constraint in the xdc.

 
  set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports {  Rx_raspi  }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
  set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { Tx_raspi }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
 


cheers,

Jon

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When I get this it is usually the uppercase/lowercase of the top level signals doens't match those used in the .XDC file. This is the only place case matters in a VHDL project!

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On 6/2/2017 at 10:03 PM, hamster said:

When I get this it is usually the uppercase/lowercase of the top level signals doens't match those used in the .XDC file. This is the only place case matters in a VHDL project!

Yes, I confused the uppercase/lowercase of 'x' in the top level and the XDC file as I thought it didn't matter, Thank you.

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