I’ve followed the ZYBO HDMI Demo available from the Digilent website. The basic options worked fine, however when trying out 1080p I get an image that appears to be bouncing up and down a bit. This is very annoying and undesired.
Vivado gives the following critical warining when running the implementation:
[DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell hdmi_in_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator. The computed FVCO is 599.952 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 5.000, CLKIN1_PERIOD = 8.33400, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
This violation may be corrected by:
1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run. Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range.
2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range.
3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range.
4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin.
This only occurs when the TMDS clock range op the dvi2rgb IP core is changed from < 120 MHz to >= 120 MHz (1080p) and 1920x1080 selected as my preferred resolution. I also selected 1080p as the default video mode for the video timing controller that goes to the output.
From this critical warning it appears to be a clocking error.
I also checked out the DVI_ClkGenerator that is referenced in the warning, which explains that MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result in a correct VCO frequency for 1080p. Changing values in this component doesn’t seem to have any effect. CLKIN1_PERIOD is always 8.334, even when I change its value in the generic map.
So, I’m wondering what I need to change to be able to display 1080p streams correctly?
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zybo5
Hi,
I’ve followed the ZYBO HDMI Demo available from the Digilent website. The basic options worked fine, however when trying out 1080p I get an image that appears to be bouncing up and down a bit. This is very annoying and undesired.
Vivado gives the following critical warining when running the implementation:
[DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell hdmi_in_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator. The computed FVCO is 599.952 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 5.000, CLKIN1_PERIOD = 8.33400, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)). This violation may be corrected by: 1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run. Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range. 2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range. 3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range. 4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin.This only occurs when the TMDS clock range op the dvi2rgb IP core is changed from < 120 MHz to >= 120 MHz (1080p) and 1920x1080 selected as my preferred resolution. I also selected 1080p as the default video mode for the video timing controller that goes to the output.
From this critical warning it appears to be a clocking error.
I also checked out the DVI_ClkGenerator that is referenced in the warning, which explains that MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result in a correct VCO frequency for 1080p. Changing values in this component doesn’t seem to have any effect. CLKIN1_PERIOD is always 8.334, even when I change its value in the generic map.
So, I’m wondering what I need to change to be able to display 1080p streams correctly?
Thanks in advance.
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