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r4d

PYNQ-Z1 GPIO Trace length and Layer stackup details

Question

Hello ! 

We are designing a high-speed bus on a PCB interfacing the Arduino/Chipkit GPIO pins onboard the PYNQ-Z1. Inorder to maximize the signal integrity parameters, we would like to optimize the trace lengths in our board based on the trace information and the layer stackup details of the PYNQ board. 

It would be really kind if someone from Digilent could share this valuable information to assist our optimization. 

Regards,

r4d

 

Edited by r4d

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2 answers to this question

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Hi @r4d,

I have reached out to our senior layout engineer about you question and will respond back on this thread when I get a response.

thank you,

Jon

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Hi @r4d,

Our senior layout engineer also wanted to relay that the shield connectors are not intended for high speed signals. They are intended for 50Mhz or less. I have attached is a signal length report. It is 50-52.4 characteristic impedance with 200 ohm resistors in series.  This is not good for most high speed signals. These lengths do not include package delays as they were not intended to be delay matched.

cheers,

Jon

PYNQ CK signal lengths.txt

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