I2C protocol analyzer fails with clock stretching

[russan]

I'm working with a sensor that uses clock stretching to tell the master when data is ready. When using the AD2 as an I2C master, the analyzer insists there's a NACK after an address somewhere, but I can't see where.

The first attached picture shows a write to 0x40, ACK, 0xF1, restart, read from 0x40, ACK, then slave holds both SCL and SDA low. About 68ms later (seen in the second attached picture), the slave releases the bus indicating the data is ready. The protocol analyzer shows the correct sequence from its point of view, then shows "NACK after address" even though all bytes were clearly ACK'd. From what I can tell, I'm using everything correctly. Does WaveForms 2015 actually support I2C clock stretching when acting as an I2C master?

As a matter of curiosity, you might be wondering why I chose to use an analog analyzer to view the I2C lines. That's because I can't seem to coerce the logic analyzer to behave while I was also using the protocol analyzer. Is that a software limitation, a bug, or am I just using it wrong?

[attila]

Hi @russan

Unfortunately clock stretching is not supported, but I will try to add support for this in the next software version. 

The Protocol interface takes control over the device Patterns and Logic resources, so these can't be used simultaneously, except in Debug mode when it only uses the Patterns resource.

[jpeyron]

Hi @russan,

Welcome to the forum. I am tagging the engineer that will be able to give you the best response to you question( @attila).

thank you,

Jon

[russan]

Hey @attila

That would be awesome. Thanks. How often are software versions released?