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Maciej Piechotka

New user - problem finding documentation

Question

Hi,

I'm new to FPGAs and I have trouble finding documentation. In particular:

  • How exactly VSync and HSync is handled for HDMI input? What can I assume about them?
  • I'd like to create a AXI Master to store input in DDR. However I cannot find a reference for AXI4M_bus_port - how is timing handled for write_burst?
  • Are there any guaranteed on ordering of stores through AXI Master to DDR?

Matt

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@Maciej Piechotka,

I'll give you the best answers I can, but you might find them insufficient for what you are looking for.

You can find a specification for the HDMI standard here.  That said, I'm still working through building my own HDMI controller.  Getting to the VSync and HSync signals from the HDMI signal has taken me a bit of work (30+hrs).  If what you would like to do is just learn what these signals are, then I'd suggest you google VGA controller tutorials.  For example, here's one that discusses the meanings of those signals and a touch of the history behind them.  I personally got started with the VGA on the Basys-3 board, and Digilent's documentation helped me understand these two signals there.

As for your AXI questions, I think you'll find them answered in the AXI spec, here.  That should answer both of your latter questions.

If you find the AXI bus a bear to work with to get access to that memory, there are other options.  I personally use the Wishbone bus, version B4, in it's pipelined configuration.  However, you'll need to convert from Wishbone to AXI in order to use the MIG controller.  You can find a demo project, not using HDMI but using the DDR memory, here.  You can also find some of the scraps of my current HDMI work (it hasn't been paid for yet ...) here.  (I *just* managed to get an automatic synchronization routing working too ...)  I still need to connect up the memory, though, for my own work.

Holler if you have more questions,

Dan

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@D@n Thanks. I know what the signal are and why they were needed. For now I hoped to avoid and use ready components such as Digilent dvi2rgb.

With regard to AXI - sorry I haven't clarified. I was hoping to use SystemC Xilinx abstraction and library which has AXI4M_bus_port - but no real description of how it behaves. I have read the spec. Similarly I need to use it in a sense as on Zybo board memory is exposed as 4+1 AXI Slave interfaces.

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Hi @Maciej Piechotka,

To see how we work with the dvi2rgb Here and here are the HDMI-IN and HDMI-OUT for the Zybo using Vivado 2016.4.   HDMI-OUT for Vivado 2015.4 and HDMI-IN for vivado 2016.2 here

cheers,

Jon

Edited by jpeyron

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Thanks @jpeyron. I know about those examples but, well, examples are not reference documentation. I didn't know about Video In to AXI Stream component but even building atop the example I would need to know how to program the VDMA and since I want to access frames in different way then write them it doesn't fully help.

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@jpeyron I know those documents. However after reading them many times I find them both too detailed and underspecified. For example:

  • I assume the format is RGB not RBG (as documented) on output. Otherwise both IP and interface are misnamed.
  • It still don't answer if the VSYNC is kept high through the whole period or is it a pulse?
  • With regard to VDMA what format is it stored in? I assume it is just a bitmap but are RGB aligned to 1 byte (3 byte addressing) or 4 bytes [After a though - AXI is power of 2 so it must be 32-bit aligned]?
  • What happens if the data is shorter then VSIZE or HSIZE [EDIT: It seems that it sends VDMAIntErr]? I assume it goes to next stride (EDIT: no it does not] but is it possible to recover original resolution or do I need to count manually?
  • What is memory coherence when using SoC HS Axi by VDMA. I assume, though I haven't found it documented anywhere, that HS AXI will reply on BRESP after it hits data accessible by other ports and CPU (assuming that non-cached access is used). In other words if there is write W1 and read R1 the R1 happens-after W1 (in memory model sense) iff BRESP for W1 has been issued. But does the VDMA waits synchronously on it before proceeding to next frame [i.e. is there a system membar between frames]?

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