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Zybo: rom block addressing


s224071

Question

Hello everybody,

I'm developing a project using a Zybo Board. I'm on an early stage, right now I'm just trying to print out on a screen 640x480 an image from a rom memory (depth 1024, width 12) created using the Core Generator (I'm writing the project in Xilinx ISE 14.7). However, the result on the screen is not what I expected...

First of all, I've created my rom memory containing the image: it has been converted in bitmap format and then translated to a vector of 32*32  cells (the image is 32x32 pixels), each one containing a string of 12 bits representing the color of a pixel, using a program in C, written by one of my colleagues for his own project (therefore the error very likely is not generated in this phase).  The vector resulting from this conversion has been inserted in the coe file to initialize the memory.

Coming to the project top module, it takes the image from the rom, accessing the cell that corresponds to the color of the current pixel (the 12 bits vector) and  prints it over the screen using a VGA working with 12 bits (4 R 4 G 4 B ) . The image is printed everytime hcount and vcount are multiple of 32. 

Neither synthesize nor implement design produce errors or warnings, but when I connect the Vga of the programmed Zybo to the screen, what I get is the picture in the attachments, instead of a repeated pattern of "donkey kong" (second picture).

Can somebody help me to figure out what I'm doing wrong? I include the whole project.

top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity TOP is
    Port(
        clk    : in  STD_LOGIC;
        hsync    : out  STD_LOGIC;
        vsync    : out  STD_LOGIC;
        red    : out  STD_LOGIC_VECTOR (3 downto 0);
        green    : out  STD_LOGIC_VECTOR (3 downto 0);
        blue    : out  STD_LOGIC_VECTOR (3 downto 0)
    );
end TOP;

architecture Behavioral of TOP is
    
    --clock a 25 MHz
    component clk_div
        port
         (-- Clock in ports
          CLK_IN1           : in     std_logic;
          -- Clock out ports
          CLK_OUT1          : out    std_logic
         );
    end component;
    
    component donkey_rom
       port (  CLKA : in  STD_LOGIC;
              ADDRA: in  STD_LOGIC_VECTOR (9 downto 0);
              DOUTA : out  STD_LOGIC_VECTOR (11 downto 0)
             );
    end component;

  component Counter_RC
        port(
            clk25 : in  STD_LOGIC;
         hcount : out  STD_LOGIC_VECTOR (9 downto 0);
         vcount : out  STD_LOGIC_VECTOR (9 downto 0)
        );
    end component;
    
    component VGA
        port
        (
            clk25     : in  STD_LOGIC;
            hsync_m     : out  STD_LOGIC;
         vsync_m     : out  STD_LOGIC;
         rosso     : out  STD_LOGIC_VECTOR (3 downto 0);
         verde     : out  STD_LOGIC_VECTOR (3 downto 0);
         blu         : out  STD_LOGIC_VECTOR (3 downto 0);
            data         : in STD_LOGIC_VECTOR (11 downto 0);
            hcount     : in STD_LOGIC_VECTOR (9 downto 0);
            vcount     : in STD_LOGIC_VECTOR (9 downto 0)
        );
    end component;
    
    signal clk_cm : STD_LOGIC;
    signal data_out: STD_LOGIC_VECTOR (11 downto 0);
    signal h : STD_LOGIC_VECTOR (9 downto 0);
    signal v : STD_LOGIC_VECTOR (9 downto 0);
    signal vga_hs : STD_LOGIC;
    signal vga_vs : STD_LOGIC;
    signal vga_red : STD_LOGIC_VECTOR (3 downto 0);
    signal vga_green : STD_LOGIC_VECTOR (3 downto 0);
    signal vga_blue : STD_LOGIC_VECTOR (3 downto 0);
    signal address: STD_LOGIC_VECTOR (9 downto 0);
    
    begin 
    
     dcm25 : clk_div
      port map
        (-- Clock in ports
         CLK_IN1 => clk,
         -- Clock out ports
         CLK_OUT1 => clk_cm
      );
      
      Rom : donkey_rom
        port map(
            CLKA    => clk_cm,
         DOUTA => data_out,
            ADDRA => address
          );
    
          Screen : VGA
        port map(
            clk25     => clk_cm,
            hsync_m     => vga_hs,
         vsync_m     => vga_vs,
         rosso     => vga_red,
         verde     => vga_green,
         blu         => vga_blue,
            data         => data_out,
            hcount     => h,
            vcount     => v
        );
        
    CounterRC : Counter_RC
        port map(
            clk25     => clk_cm,
            hcount     => h,
            vcount     => v
        );
        
        process(clk_cm)
           begin
               if rising_edge(clk_cm) then
                 if to_integer(unsigned(h))<640 and to_integer(unsigned(v))<480 then
                address<=std_logic_vector(to_unsigned(((to_integer(unsigned(v))mod 32)*32 +(to_integer(unsigned(h))) mod 32), 10));                
               end if;
                end if;
        end process;
            red <= vga_red;
            green <= vga_green;
            blue <= vga_blue;
            vsync <= vga_vs;
            hsync <= vga_hs;
            
            
end Behavioral;
 

vga.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity VGA is
    port
    (
        clk25 : in  STD_LOGIC;
        hsync_m : out  STD_LOGIC;
        vsync_m : out  STD_LOGIC;
        rosso : out  STD_LOGIC_VECTOR (3 downto 0);
        verde : out  STD_LOGIC_VECTOR (3 downto 0);
        blu : out  STD_LOGIC_VECTOR (3 downto 0);
        data : in STD_LOGIC_VECTOR (11 downto 0);
        hcount : in STD_LOGIC_VECTOR (9 downto 0);
        vcount : in STD_LOGIC_VECTOR (9 downto 0)
    );
end VGA;

architecture Behavioral of VGA is

    

begin
        
    process(clk25, data)
        
    begin
        if rising_edge(clk25) then
            
            --Vsync
            if vcount > 489 and vcount < 492 then
                vsync_m <= '0';
            else
                vsync_m <= '1';
            end if;
            
            --Hsync
            if hcount >= 656 and hcount < 752 then
                hsync_m <= '0';
            else
                hsync_m <= '1';
            end if;
            
        end if;
        
        --Output su schermo
        rosso <= data(11 downto 8);
        verde <= data(7 downto 4);
        blu <= data(3 downto 0);
            
    end process;

end Behavioral;
 

RC.vhd --counter for vga synchr signals

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter_RC is
    Port ( clk25 : in  STD_LOGIC;
           hcount : out  STD_LOGIC_VECTOR (9 downto 0);
           vcount : out  STD_LOGIC_VECTOR (9 downto 0)
            );
end Counter_RC;


architecture Behavioral of Counter_RC is

begin
    
    process(clk25)
        --Counter usati: v sono le righe, h le colonne
        variable v: natural range 0 to 524 := 0;
        variable h: natural range 0 to 799 := 0;
        
    begin
        
        if rising_edge(clk25) then
            --incremento i counter
            if h = 799 then
                h := 0;
                if v = 524 then
                    v := 0;
                else
                    v := v + 1;
                end if;
            else
                h := h + 1;
            end if;
            
            --li propago
            hcount <= std_logic_vector(to_unsigned(h, 10));
            vcount <= std_logic_vector(to_unsigned(v, 10));
        end if;
    
    end process;

end Behavioral;

 

pin.ucf


 NET "clk"   LOC = "L16" | IOSTANDARD=LVCMOS33;

# NET "SW_I"   LOC = "U9" | IOSTANDARD=LVCMOS33;

# NET "LED_O<0>"   LOC = "T8" | IOSTANDARD=LVCMOS33;
# NET "LED_O<1>"   LOC = "V9" | IOSTANDARD=LVCMOS33;
# NET "LED_O<2>"   LOC = "R8" | IOSTANDARD=LVCMOS33;
# NET "LED_O<3>"   LOC = "T6" | IOSTANDARD=LVCMOS33;
# NET "LED_O<4>"   LOC = "T5" | IOSTANDARD=LVCMOS33;
# NET "LED_O<5>"   LOC = "T4" | IOSTANDARD=LVCMOS33;
# NET "LED_O<6>"   LOC = "U7" | IOSTANDARD=LVCMOS33;
# NET "LED_O<7>"   LOC = "U6" | IOSTANDARD=LVCMOS33;

# NET "LED_H_O<0>"   LOC = "R1" | IOSTANDARD=LVCMOS33;
# NET "LED_H_O<1>"   LOC = "P5" | IOSTANDARD=LVCMOS33;
# NET "LED_H_O<2>"   LOC = "U1" | IOSTANDARD=LVCMOS33;
# NET "LED_H_O<3>"   LOC = "R2" | IOSTANDARD=LVCMOS33;
# NET "LED_H_O<4>"   LOC = "P2" | IOSTANDARD=LVCMOS33;
 
## VGA Connector
NET "red<0>"        LOC=M19 | IOSTANDARD=LVCMOS33; #IO_L7P_T1_AD2P_35
NET "red<1>"        LOC=L20 | IOSTANDARD=LVCMOS33; #IO_L9N_T1_DQS_AD3N_35
NET "red<2>"        LOC=J20 | IOSTANDARD=LVCMOS33; #IO_L17P_T2_AD5P_35
NET "red<3>"        LOC=G20 | IOSTANDARD=LVCMOS33; #IO_L18N_T2_AD13N_35
#NET "red<4>"        LOC=F19 | IOSTANDARD=LVCMOS33; #IO_L15P_T2_DQS_AD12P_35
NET "green<0>"        LOC=H18 | IOSTANDARD=LVCMOS33; #IO_L14N_T2_AD4N_SRCC_35
NET "green<1>"        LOC=N20 | IOSTANDARD=LVCMOS33; #IO_L14P_T2_SRCC_34
NET "green<2>"        LOC=L19 | IOSTANDARD=LVCMOS33; #IO_L9P_T1_DQS_AD3P_35
NET "green<3>"        LOC=J19 | IOSTANDARD=LVCMOS33; #IO_L10N_T1_AD11N_35
#NET "green<4>"        LOC=H20 | IOSTANDARD=LVCMOS33; #IO_L17N_T2_AD5N_35
#NET "green<5>"        LOC=F20 | IOSTANDARD=LVCMOS33; #IO_L15N_T2_DQS_AD12N_35
NET "blue<0>"        LOC=P20 | IOSTANDARD=LVCMOS33; #IO_L14N_T2_SRCC_34
NET "blue<1>"        LOC=M20 | IOSTANDARD=LVCMOS33; #IO_L7N_T1_AD2N_35
NET "blue<2>"        LOC=K19 | IOSTANDARD=LVCMOS33; #IO_L10P_T1_AD11P_35
NET "blue<3>"        LOC=J18 | IOSTANDARD=LVCMOS33; #IO_L14P_T2_AD4P_SRCC_35
#NET "blue<4>"        LOC=G19 | IOSTANDARD=LVCMOS33; #IO_L18P_T2_AD13P_35
NET "hsync"        LOC=P19 | IOSTANDARD=LVCMOS33; #IO_L13N_T2_MRCC_34
NET "vsync"        LOC=R19 | IOSTANDARD=LVCMOS33; #IO_0_34
 

photo_2017-05-15_20-28-55.jpg

donkey.bmp

definition1_donkey.coe

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Sorry, I was just thinking out loud.. Actually, I'm working on a similar project, maybe I can help. I'm not printing donkey kong but rather the nazi flag hehe (for teh lulz). Is your VGA code working correctly, you've made simple patterns on the screen using some algorithm rather than reading a memory?

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