BRAM resource

[Reinaldo Götz]

Hello!

I'm a begginer in FPGA, designing a project with Xilinx LogiCORE FIR Compiler in a Digilent Cmod A7-35T board.

The filter has 256 sets of coefficients (256 interleaved channels). The problem is that the use of BRAMs exceeds the resources available in the device.

Is it possible to increase the BRAMs number with the cellular RAM available in the Cmod board?

Thanks.

Reinaldo

 

[D@n]

@Reinaldo Götz,

Perhaps.  You might struggle to do it with the FIR compiler, and you may find that it depends upon the data rate of the signal you are working with.

256 channels?  at 256 taps each?  Ouch.  That's a tall spec.  Doable?  Perhaps.  Might take some work on your part.  (i.e., not the FIR compiler which attempts to produce a one-size fits all solution that ... never really fits all.  For example, I don't think the FIR compiler would ever use that SRAM, but you can build your own.)

What are you trying to accomplish, if you don't mind my asking?

Dan

[Reinaldo Götz]

Thank you for your prompt reply, Dan.

I see. The AXI-Stream based FIR compiler core cannot access SRAM.

I'm testing the filter throughput and I'm building an interface between any (large) set of signals and the FIR compiler, taking into account the filter select value for each interleaved data channel at 44.1 kHz.

Reinaldo