Digilent Genesys LVPECL Differential Clock

[ee_engineer]

Hello there,

I am working with a Digilent Genesys Virtex-5 Development Board and want to implement an LVPECL output clock.  The Genesys 1 board has a Virtex-5, which supports LVPECL, but I cannot find the LVPECL output on the Genesys 1? 

Looking through Genesys 1 board schematics, I could not find LVPECL_25 outputs as seen in the Virtex-5 FPGA User Guide.  

 

[elodg]

According to ug190 pg. 297 a LVPECL-compliant transmitter needs a three-resistor output termination circuit that is not present on the Genesys. A further requirement from pg. 299 is the 2.5V bank supply voltage, which is available in bank 3, 12 and selectable on 11, 13. Banks 11 and 13 are the ones wired to the VHDCI connectors and your best bet is creating a custom board or using something like http://store.digilentinc.com/all-products/modules-add-on-boards/vmod-vhdci-expansion-modules/ to get your signal out of the board and add the termination resistor. It is not ideal, because it won't be near-end anymore, but it might work.