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soha

use Pmod in Zedboard

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Hi,

I have loaded a Linaro Ubuntu on the Zedboard using Vivado 2016.2 and I want to extract the CoreSight trace data off the board. By applying the same idea suggested in the link http://blog.idv-tech.com/2014/03/22/howto-export-zynq-peripheralsi2c-spi-uart-and-etc-to-pmod-connectors-of-zedboard-using-vivado-2013-4/ , I enabled CoreSight component in the block customization of the Zynq PS, mapped its IO to EMIO, made the TRACE_0 external, and changed my .XDC file to map the 8-bit output data to the JA1 PMOD data pins. However, I'm not sure with my next step. When I powered on my board and tried to use Tera Term to monitor the Pmod port, Tera Term cannot even detect the COM port. So what I'm missing here? It seems that it is not as straightforward as just plug-in-and-use. Do I need some specific IP core or write a driver in the OS to make this work?

I think what I want to do is just to offload some data through the PL-side Pmod and monitor it using Tera Term. I believe this can be done without much pain. So is there tutorial outside for that? Thanks in advance.

P.S. Does Digilent provide any Pmod-to-USB converter which supports 2x6 pinouts? If yes, can anyone provide a link for that?

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Hi @soha,

I do not have any experience with coresight as we discussed earlier on you previous post here. Although I think you should be using the JE port for the emio pins. I did find an older link for mio to emio for the zedboard here.  As far as I am aware we only have a 1x6 pmod here.

cheers,

Jon

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On 5/10/2017 at 6:13 PM, jpeyron said:

Hi @soha,

I do not have any experience with coresight as we discussed earlier on you previous post here. Although I think you should be using the JE port for the emio pins. I did find an older link for mio to emio for the zedboard here.  As far as I am aware we only have a 1x6 pmod here.

cheers,

Jon

 
 
 

Hi @jpeyron,

Thanks for your reply. I think the trace port from CoreSight is quite similar as other I/O peripheral like UART, SPI, etc. and can be mapped through either MIO or EMIO, as the block diagram below shows.

Capture.JPG

I know JE Pmod is the PS-side Pmod and I think this is why you suggest to use it. But it seems that some of the JE Pmod pins has been occupied by some other peripheral and I think if you map the I/O peripheral through EMIO, you can only map it to PL-side Pmod, right? That's why I'm trying to use PL-side Pmod. What actually confused me is what the requirement is to make the mapping work (i.e. I can at least monitor some output using software like Tera Term). From the link I posted in my question and the link you just posted, there is no additional effort needed to be taken other than making the port external and writing appropriate mapping in the .XDC file. However, there is no output can be caught after I burn the board. I must miss something here, while I really have no idea about it. So what is the standard flow to extract signals off the board from the interface like Pmod or JTAG? I will really appreciate it if there is any clear instruction/tutorial/explanation. Thanks in advance.

Soha

Edited by soha

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Hi @soha

I was able to get signals from JB on my o-scope with traces set to JB. I found a xilinx Setup the TRACE port via EMIO here that has you connect a FCLK_CLK0/2 in my case a second clock FCLK_CLK1  at 50 Mhz to the trace_clk_in. I then connected the trace clock out,control, data(2 pins) to port JB using the xdc. I also had gpio switchs and leds connected with sdk code running them. I have attached screen shots and my project in Vivado 2016.4 below. Hopefully this gets you started in the right path. 

cheers,

Jon  

coresight.zip

coresight_o-scope.jpg

coresight_vivado_block_design.jpg

Edited by jpeyron

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On 5/12/2017 at 7:30 PM, jpeyron said:

Hi @soha

I was able to get signals from JB on my o-scope with traces set to JB. I found a xilinx Setup the TRACE port via EMIO here that has you connect a FCLK_CLK0/2 in my case a second clock FCLK_CLK1  at 50 Mhz to the trace_clk_in. I then connected the trace clock out,control, data(2 pins) to port JB using the xdc. I also had gpio switchs and leds connected with sdk code running them. I have attached screen shots and my project in Vivado 2016.4 below. Hopefully this gets you started in the right path. 

cheers,

Jon  

coresight.zip

coresight_o-scope.jpg

coresight_vivado_block_design.jpg

 

Hi @jpeyron,

Thanks for your reply. I think the reason why I cannot get it work previously is that I didn't connect the clock input to the trace I/O. I thought there is an intrinsic clock signal in the PS that drives the trace module by default. Currently, I still cannot see my output in the COM monitoring terminal on my PC. Probably there is some driver-related problem. Unfortunately, I don't have o-scope by my side now so I am not able to physically touch the pin. In any case, I believe the FPGA-side work should be just as what you suggested. Thanks for your help!

Best,

soha

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