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SDK 2016.4 Debug Error


vinod.sajjan

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Hi Folks,

I am working with Xilinx Zynq7020 SOC Chip.

Also, I am using Digilent JTAG-HS3 Jtag.

I made design in vivado 2015.2 and HLS IP block also made in Vivado HLS 2015.2, design is checked in SDK 2015.2 is working fine.

 

Presently, i upgraded to 2016.4 vivado package and upgraded the 2015.2 design to 2016.4.

 

validates the design and generate bit stream in 2016.4.

 

Running the design in SDK 2016.4 with source (C) files.

 

Initially i restored the image into DDR3 physical address location, in SDK Log showing restore successfully,After as soon as this error showing (in Attached image),without running the code . 

I checked with different PC's also, same error.

what is this problem and i am unable to understand it. whether the problem with Tool or with my design .

Please find the attachment.

 

Please suggest me the solution  regarding this Problem.

 

Thanks and Best Regards

Vinod Sajjan

 

 

 

error.png

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Hi @vinod.sajjan,

Unfortunately, I do not have much experience with HLS. I reached out to the design engineer that is the most experienced with the JTAG-HS3. They had not seen these type of errors before. The SDK errors are internal xilinx error codes that we would not be able to look up to see what the issue is. I would suggest to continue with the xilinx forum thread you posted here

cheers,

Jon

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Hi @vinod.sajjan,

Our design engineer and I have not been able to find any information about these errors. The 2 errors c 166 and c 168 are internal error codes to SDK that Xilinx should be able to look up and tell you what those error codes mean.  From a trouble shooting stand point I would suggest to download Adept 2 here and confirm that the JTAG-HS3 can see the Xilinx Zynq7020 in the scan chain. I would also make a very basic project in HLS that uses all of the components and try to get that working. This should help you to narrow down where the issue is.

thank you,

Jon

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