genesys2 flash problem (help me pls..)

[spike556]

i am a student.

my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification)

i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that.

but the instruction is always 0x00000000 !!

(i used chipscope to detect the signal)

(i used startupe2 to access CCLK)

it seems like i didn't access the flash, can anyone help me?

thanks a lot !!

pls save me....

[D@n]

@spike556,

Looking up the Genesys2 XDC file, I notice that W19 is the fan PWM control port.  I also notice that there is no CCLK reference within the XDC file.  This is the same as what I have on my own example (Basys3 board), so ... you aren't putting the SPI SCK into the XDC file, are you?

Dan

[spike556]

thanks again. i checked my startupe2, it is the same as yours. but in vivado IO report, it connected to a pin which is not CCLK pin.

i don't know whether it will access the clk of flash after configuration

W19        | spi_sck              | High Range       | IO_25_14                     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |           | UNFIXED    |           |          |      | NONE             |

thanks for your kind help! You are great.

[D@n]

@spike556,

If your concern is the STARTUPE2 primitive, you can find an example of how to use it within the flash configuration file of my AutoFPGA project.  Look at how the @TOP.INSERT key is defined, as AutoFPGA will copy that key's definition directly into the top level Verilog file it creates.

Dan

[spike556]

thanks again ~ i will take a look

[D@n]

@spike556,

If you look hard at the OpenArty project, or even the S6SoC project (depending upon which flash you have), you will not only find a flash controller but also a flash simulator that can be used with Verilator.  Indeed, there's a UART simulator as well that decodes and encodes your UART wires, bridging them to either stdin/stdout or a  TCP/IP channel to where you might have a "console" into your "RISC-V" simulation from another computer--if that's what you wish.  (There's even a simulator of a SPI mode SD-card, should your development take you that far.)

I think you will find these tools valuable.  They will allow you to test your logic (both CPU and flash controller) without using Xilinx and the chipscope, and to get whatever access into your code and the bits flying back and forth that you might like.  My personal approach would be to avoid Xilinx until I know everything is running in the simulator, just because it can be so much more difficult to debug a design on the FPGA than it is to debug one in simulation.

Dan

[spike556]

this is what the documentation of genesys2 says

[spike556]

thanks a lot !  i will clear my situation

1 . thanks , i will take a look

2.  thanks.

3. i can't see the command, i use vivado to program flash indirectly(not my circuit). Then i program my FPGA, when it's done, i think it will fetch instruction automatically(but i am not sure..) i simulated the flash's verilog behavior model, it worked.

4.my senior wrote the spi controller. but he is sleeping now.. i will ask him later.

5.i am not sure what address of the ID code in flash..how can i read the ID code?

(when i program the flash using vivado, i rememberd i saw the ID)

6.i think my flash and flash controller don't work, because i think i can't access the flash..

(if i access flash successfully, it can't be all zeros)

the problem is, the sck of flash in genesys2 is a dedicated pin. i don't think i access it correctly.

thanks a lot again! 

 

[D@n]

@spike556,

A couple of things ...

1. You can find an example flash controller, indeed the one I wrote and use myself, on OpenCores here.
2. The OpenArty project is somewhat similar in functionality to what you are describing above: there is a CPU on board that reads its first instruction from flash.  The CPU, though, is the ZipCPU and not the RISC-V.  Still, you might find the example instructive.
3. Looks like you are using ChipScope ... can you see what commands are being sent to the flash?  Clock?  Data?  Is the flash controller properly resetting the flash before reading it, or are you starting in whatever state the FPGA left it in on startup?
4. Not sure if you are using someone else's flash controller or your own, but ... there's a lot of details that need to take place on such a controller just to get it to a place where it can be read.  For example, is your controller and the on-board flash both in sync regarding whether they are in SPI mode or QSPI mode?  The transition needs to be made between the two.  Has QSPI mode been enabled within the flash?  Has it gotten stuck in XIP mode?  When you look at things through ChipScope, go ahead and look for these details as well.
5. Usually, my first attempt to read from a flash involves reading the ID code from the flash.  This proves to me that I can actually talk to the flash, and that it responds.  Are you able to read the ID code from the flash at all?
6. The other thing I usually do is test all of the peripherals manually before I try starting the CPU up.  To do this, I issue commands externally--such as from a UART or even JTAG port.  Only once the peripheral has been manually verified do I ever try to use it with the CPU.  Have you manually verified that both your flash and flash controller are working successfully and successfully together apart from the CPU?

Dan