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spike556

genesys2 flash problem (help me pls..)

Question

i am a student.

my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification)

i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that.

but the instruction is always 0x00000000 !!

(i used chipscope to detect the signal)

(i used startupe2 to access CCLK)

it seems like i didn't access the flash, can anyone help me?

thanks a lot !!

pls save me....

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@spike556,

A couple of things ...

  1. You can find an example flash controller, indeed the one I wrote and use myself, on OpenCores here.
  2. The OpenArty project is somewhat similar in functionality to what you are describing above: there is a CPU on board that reads its first instruction from flash.  The CPU, though, is the ZipCPU and not the RISC-V.  Still, you might find the example instructive.
  3. Looks like you are using ChipScope ... can you see what commands are being sent to the flash?  Clock?  Data?  Is the flash controller properly resetting the flash before reading it, or are you starting in whatever state the FPGA left it in on startup?
  4. Not sure if you are using someone else's flash controller or your own, but ... there's a lot of details that need to take place on such a controller just to get it to a place where it can be read.  For example, is your controller and the on-board flash both in sync regarding whether they are in SPI mode or QSPI mode?  The transition needs to be made between the two.  Has QSPI mode been enabled within the flash?  Has it gotten stuck in XIP mode?  When you look at things through ChipScope, go ahead and look for these details as well.
  5. Usually, my first attempt to read from a flash involves reading the ID code from the flash.  This proves to me that I can actually talk to the flash, and that it responds.  Are you able to read the ID code from the flash at all?
  6. The other thing I usually do is test all of the peripherals manually before I try starting the CPU up.  To do this, I issue commands externally--such as from a UART or even JTAG port.  Only once the peripheral has been manually verified do I ever try to use it with the CPU.  Have you manually verified that both your flash and flash controller are working successfully and successfully together apart from the CPU?

Dan

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thanks a lot !  i will clear my situation

1 . thanks , i will take a look

2.  thanks.

3. i can't see the command, i use vivado to program flash indirectly(not my circuit). Then i program my FPGA, when it's done, i think it will fetch instruction automatically(but i am not sure..) i simulated the flash's verilog behavior model, it worked.

4.my senior wrote the spi controller. but he is sleeping now.. i will ask him later.

5.i am not sure what address of the ID code in flash..how can i read the ID code?

(when i program the flash using vivado, i rememberd i saw the ID)

6.i think my flash and flash controller don't work, because i think i can't access the flash..

(if i access flash successfully, it can't be all zeros)

the problem is, the sck of flash in genesys2 is a dedicated pin. i don't think i access it correctly.

thanks a lot again! 

 

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@spike556,

If you look hard at the OpenArty project, or even the S6SoC project (depending upon which flash you have), you will not only find a flash controller but also a flash simulator that can be used with Verilator.  Indeed, there's a UART simulator as well that decodes and encodes your UART wires, bridging them to either stdin/stdout or a  TCP/IP channel to where you might have a "console" into your "RISC-V" simulation from another computer--if that's what you wish.  (There's even a simulator of a SPI mode SD-card, should your development take you that far.)

I think you will find these tools valuable.  They will allow you to test your logic (both CPU and flash controller) without using Xilinx and the chipscope, and to get whatever access into your code and the bits flying back and forth that you might like.  My personal approach would be to avoid Xilinx until I know everything is running in the simulator, just because it can be so much more difficult to debug a design on the FPGA than it is to debug one in simulation.

Dan

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thanks again. i checked my startupe2, it is the same as yours. but in vivado IO report, it connected to a pin which is not CCLK pin.

i don't know whether it will access the clk of flash after configuration

W19        | spi_sck              | High Range       | IO_25_14                     | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |           | UNFIXED    |           |          |      | NONE             |

thanks for your kind help! You are great.

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@spike556,

Looking up the Genesys2 XDC file, I notice that W19 is the fan PWM control port.  I also notice that there is no CCLK reference within the XDC file.  This is the same as what I have on my own example (Basys3 board), so ... you aren't putting the SPI SCK into the XDC file, are you?

Dan

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yes..because i don't know how to constrain it...

in xdc, it didn't tell me  how to constraint the spi_sck..

## QSPI
  #set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
  #set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
  #set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1]
  #set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2]
  #set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3]

 

thanks for your kind help. pls help me again..

 

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@spike556,

Not sure if I was clear enough: Do not place the SPI SCK pin into the XDC file.  Trying to place it there would be a mistake, as the pin is already constrained.  There is only one CCLK pin, the pin is fixed by the FPGA manufacturer, and you just need to use it.  You don't want the pin in the XDC file.  It should not appear in your top level port list.  It only appears in the STARTUPE2 primitive.  That's how you get access to it.

Dan

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thanks a lot!

thank you!

i am not a native English speaker, so i didn't get it.... sorry

thanks again! it's so kind of you to help me

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@D@n

"It should not appear in your top level port list.  It only appears in the STARTUPE2 primitive."

you mean spi_sck can't be an output of top module?

and besides startupe2, spi_sck maybe appears in spi_controller?(because it generates spi_sck..)

(i know these questions are silly, forgive me...)

anyway, thanks a lot~

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@spike556,

That is correct.  spi_sck cannot and should not be in your top level port list.  It should come from the controller, and go into the STARTUPE2 primitive.  STARTUPE2 will place it on the FPGA pin for you.

Dan

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@spike556,

Does that mean that you found your final bug?  Or just one in a long series/process of getting your design up and running?  ;)

Can I convince you to come back and post your project in the Project Vault once you complete it?

Dan

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@D@n

i really don't know whether it's my final bug..

i am sorry. The code wasn't written by me, my seniors and teathers wrote it.i can't post it right now..i don't have the power..

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@D@n

when our paper is published.

I will ask my teacher's permission, if i get the permission, i will post it.

A word can never be withdrawn。

thanks again!

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@D@n

still don't work..

i used an oscillograph to detect the spi_sck and IO0 pin outside the flash, they seem right.

but there is no signal in IO1(it remains zero)

how can this be?.. (probably flash is broken?)

Can you help me?

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@spike556,

Can you program a configuration into the flash and read it on startup?  Perhaps something that just blinks an LED?  If so, your flash isn't broken.  Even better, if you do the configuration via the 4-wire QSPI protocol, then you'll know that all the wires are working and present.

Have you tried your code with a flash simulator to know if it works or not?  That would give you much more access into knowing what's going wrong.

Dan

 

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@D@n

sorry for replying you late.

Thanks for your advice. Yes, i do the configuration via QSPI successfully when my configuration mode is in QSPI mode.(does this mean i can only access flash when my configuration mode is in QSPI mode?)

i have tried my code in flash behavior verilog model provided by the manufacture .it works fine.(s25fl256.v) 

 

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