spike556 Posted May 4, 2017 Share Posted May 4, 2017 i am a student. my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification) i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that. but the instruction is always 0x00000000 !! (i used chipscope to detect the signal) (i used startupe2 to access CCLK) it seems like i didn't access the flash, can anyone help me? thanks a lot !! pls save me.... Link to comment Share on other sites More sharing options...
spike556 Posted May 6, 2017 Author Share Posted May 6, 2017 @D@n sorry for replying you late. Thanks for your advice. Yes, i do the configuration via QSPI successfully when my configuration mode is in QSPI mode.(does this mean i can only access flash when my configuration mode is in QSPI mode?) i have tried my code in flash behavior verilog model provided by the manufacture .it works fine.(s25fl256.v) Link to comment Share on other sites More sharing options...
D@n Posted May 4, 2017 Share Posted May 4, 2017 @spike556, Does that mean that you found your final bug? Or just one in a long series/process of getting your design up and running? Can I convince you to come back and post your project in the Project Vault once you complete it? Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 @D@n i really don't know whether it's my final bug.. i am sorry. The code wasn't written by me, my seniors and teathers wrote it.i can't post it right now..i don't have the power.. Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 @D@n when our paper is published. I will ask my teacher's permission, if i get the permission, i will post it. A word can never be withdrawn。 thanks again! Link to comment Share on other sites More sharing options...
D@n Posted May 4, 2017 Share Posted May 4, 2017 @spike556, How about this ... can you at least post a link to the paper when it gets published? It sounds like one that I'd love to read. Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 @D@n sure, as long as it publishes. Link to comment Share on other sites More sharing options...
spike556 Posted May 6, 2017 Author Share Posted May 6, 2017 @D@n still don't work.. i used an oscillograph to detect the spi_sck and IO0 pin outside the flash, they seem right. but there is no signal in IO1(it remains zero) how can this be?.. (probably flash is broken?) Can you help me? Link to comment Share on other sites More sharing options...
D@n Posted May 6, 2017 Share Posted May 6, 2017 @spike556, Can you program a configuration into the flash and read it on startup? Perhaps something that just blinks an LED? If so, your flash isn't broken. Even better, if you do the configuration via the 4-wire QSPI protocol, then you'll know that all the wires are working and present. Have you tried your code with a flash simulator to know if it works or not? That would give you much more access into knowing what's going wrong. Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 @D@n thanks for your patient and profession! thanks! Link to comment Share on other sites More sharing options...
D@n Posted May 6, 2017 Share Posted May 6, 2017 @spike556, Is the behavior verilog model sufficient for you to be able to boot your CPU in simulation with it? I mean .... there's a lot of stuff/steps involved in starting up a soft-core CPU on an FPGA. Is the verilog model you have sufficient to get you from power on to the first couple instructions to know that it works? Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 6, 2017 Author Share Posted May 6, 2017 we use a button to boot the cpu from flash.(our RTL code defines that) in slow mode, when we push a button,spi controller move part of data from flash to our mmu(including imem and dmem). When it finished, we read instruction from our mmu and execute it. in fast mode,when need to push a button twice to do the same(the interval is defined by the manufacture) Link to comment Share on other sites More sharing options...
spike556 Posted May 6, 2017 Author Share Posted May 6, 2017 @D@n Link to comment Share on other sites More sharing options...
D@n Posted May 6, 2017 Share Posted May 6, 2017 @spike556, Sure ... but can you simulate your way through all of that? and ... does your simulation support validating your use of the flash along the way? Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 7, 2017 Author Share Posted May 7, 2017 @D@n sorry for replying you late.. I will take a look. thanks. Link to comment Share on other sites More sharing options...
spike556 Posted May 9, 2017 Author Share Posted May 9, 2017 @D@n problem solved. Thanks a lot! Link to comment Share on other sites More sharing options...
D@n Posted May 9, 2017 Share Posted May 9, 2017 @spike556, Glad you solved it! I'm excited for your project. Did you ever manage to simulate your design from power up to first instruction? Did it help? Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 10, 2017 Author Share Posted May 10, 2017 @D@n Yes, it helped! But there were other bugs we needed to fix to correct our design. Thanks for your help and concern!. Link to comment Share on other sites More sharing options...
D@n Posted May 4, 2017 Share Posted May 4, 2017 @spike556, That is correct. spi_sck cannot and should not be in your top level port list. It should come from the controller, and go into the STARTUPE2 primitive. STARTUPE2 will place it on the FPGA pin for you. Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 @D@n "It should not appear in your top level port list. It only appears in the STARTUPE2 primitive." you mean spi_sck can't be an output of top module? and besides startupe2, spi_sck maybe appears in spi_controller?(because it generates spi_sck..) (i know these questions are silly, forgive me...) anyway, thanks a lot~ Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 @D@n Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 thanks a lot! thank you! i am not a native English speaker, so i didn't get it.... sorry thanks again! it's so kind of you to help me Link to comment Share on other sites More sharing options...
D@n Posted May 4, 2017 Share Posted May 4, 2017 @spike556, Not sure if I was clear enough: Do not place the SPI SCK pin into the XDC file. Trying to place it there would be a mistake, as the pin is already constrained. There is only one CCLK pin, the pin is fixed by the FPGA manufacturer, and you just need to use it. You don't want the pin in the XDC file. It should not appear in your top level port list. It only appears in the STARTUPE2 primitive. That's how you get access to it. Dan Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 @D@n my friend.. Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 no wonder i can somehow control the Fan... Link to comment Share on other sites More sharing options...
spike556 Posted May 4, 2017 Author Share Posted May 4, 2017 yes..because i don't know how to constrain it... in xdc, it didn't tell me how to constraint the spi_sck.. ## QSPI #set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn #set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0] #set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1] #set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2] #set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3] thanks for your kind help. pls help me again.. Link to comment Share on other sites More sharing options...
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spike556
i am a student.
my lab writes a riscv cpu core and a spi controller and they ask me to test it in FPGA.(it passed verification)
i want to access the flash to fetch instruction and CPU will execute it, at least, i expected that.
but the instruction is always 0x00000000 !!
(i used chipscope to detect the signal)
(i used startupe2 to access CCLK)
it seems like i didn't access the flash, can anyone help me?
thanks a lot !!
pls save me....
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