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lekgolo167

getting started with vivado

Question

I'm getting these errors when trying to run synthesis a demo project from the arty resource page. On that page I tired doing the XADC. i did get it to generate the .tlc file stuff to make the project I did download the board files for the arty and placed them in the boards_files directory. but maybe it's not implemented correctly or im missing something. Some xilinx forums said to click on the "open block design" to fix this but mine is grayed out and I can't select it. Most tutorials online show the old Vivado UI the 2017.1 seems to be slightly different.

mostly likely due to the missing xadc_wiz_0  module but it shows up on the source list. Or maybe its a compatibility issue between Vivado 2016.4 and 2017.4

 

I'll wait for a response before trying something else. 

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Edited by lekgolo167

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@lekgolo167

We don't currently support 2017.1, but are you able to run Report->Report IP Status in the Tools dropdown? I suspect this is a Vivado version problem, so if you can't either bring in the correct xadc_wiz IP from that .xci file, or create an identical one from the IP Catalog, I'd suggest installing 2016.4.

Thanks,

Arthur

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that's what I thought but don't the projects on here come with all the files need?

there is a xadc_wiz_0.xci file found in master/src/ip/xadca_wiz

is that the right file or does it need to be a .v file like the top module?

while the top module is found in master/src/hdl 

 

in the entire master folder thats the only file with xadc_wiz_0 so is it missing then? or is it supposed to import it from a library?

 

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I think that fixed it. In the sources window I clicked the IP Sources tab and right clicked the module and I think i selected update IP or generate IP and it seems to be running properly on the board.

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