WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
[Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267]
Opt Design
[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of type 'inst_clk/clk_wiz_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
I ran the Tcl command report_ip_status
report_ip_status
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
Question
BeamPower
Cmod A7 Out of Box Demo errors
I have the CMPD A7 with the 35T chip, so I downloaded from GITHub the project repository named:
Cmod A7 35T Project Repository
1.2) Generate the User project in the Projects folder by following this guide before continuing: How to Generate a Project from Digilent's Github
What is the User project?
Did you mean create_project.tcl?
I ran Vivado 2016.4 and started with a clean slate.
On the Tcl command line I changed directory to the Cmod A7 35T Project Repository
cd C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj/
I then ran the tcl file
source ./create_project.tcl
A new project was created.
Generate Bitstream
a warning showed up immediately
WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci
Implementation
Design Initialization
[Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267]
Opt Design
[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of type 'inst_clk/clk_wiz_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
I ran the Tcl command report_ip_status
report_ip_status
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
| Date : Fri Apr 28 14:32:28 2017
| Host : DESKTOP-7CSAO6T running 64-bit major release (build 9200)
| Command : report_ip_status
------------------------------------------------------------------------------------
IP Status Summary
1. Project IP Status
--------------------
Your project uses 1 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.
More information on the Xilinx versioning policy is available at www.xilinx.com.
Project IP Instances
+---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+
| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |
| | | | Log | | Version | | License | |
+---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+
| clk_wiz_0 | IP revision change. IP board change. IP part change | Upgrade IP | *(1) | Clocking Wizard | 5.3 | 5.3 (Rev. 3) | Included | xc7a15tcpg236-1 |
| | | | | | (Rev. | | | |
| | | | | | 1) | | | |
+---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+
*(1) c:/Xilinx/Vivado/2016.4/data/ip/xilinx/clk_wiz_v5_3/doc/clk_wiz_v5_3_changelog.txt
Now what?
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