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CMOD A7 Out of Box Demo errors


BeamPower

Question

Cmod A7 Out of Box Demo errors

I have the CMPD A7 with the 35T chip, so I downloaded from GITHub the project repository named:

    Cmod A7 35T Project Repository

1.2) Generate the User project in the Projects folder by following this guide before continuing: How to Generate a Project from Digilent's Github

What is the User project?

Did you mean create_project.tcl?

I ran Vivado 2016.4 and started with a clean slate.

On the Tcl command line I changed directory to the Cmod A7 35T Project Repository

cd C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj/

I then ran the tcl file

    source ./create_project.tcl

A new project was created.

Generate Bitstream

a warning showed up immediately

WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done.

Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.

C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci

Implementation

  • Design Initialization

  • [Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267]

  • Opt Design

  • [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of type 'inst_clk/clk_wiz_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

  • [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

 

I ran the Tcl command report_ip_status

report_ip_status

Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

------------------------------------------------------------------------------------

| Tool Version : Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016

| Date : Fri Apr 28 14:32:28 2017

| Host : DESKTOP-7CSAO6T running 64-bit major release (build 9200)

| Command : report_ip_status

------------------------------------------------------------------------------------

IP Status Summary

1. Project IP Status

--------------------

Your project uses 1 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.

More information on the Xilinx versioning policy is available at www.xilinx.com.

Project IP Instances

+---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+

| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |

| | | | Log | | Version | | License | |

+---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+

| clk_wiz_0 | IP revision change. IP board change. IP part change | Upgrade IP | *(1) | Clocking Wizard | 5.3 | 5.3 (Rev. 3) | Included | xc7a15tcpg236-1 |

| | | | | | (Rev. | | | |

| | | | | | 1) | | | |

+---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+

*(1) c:/Xilinx/Vivado/2016.4/data/ip/xilinx/clk_wiz_v5_3/doc/clk_wiz_v5_3_changelog.txt

 

Now what?

 

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4 answers to this question

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Now what?

There was a forum entry in March from jpeyron about an out of date clock wizard.

Instead of deleting and recreating the clock wizard, I saw an option to update it.

So I ran an update on the IP for clk_wiz_0

I also converted to core container format.

upgrade_ip -vlnv xilinx.com:ip:clk_wiz:5.3 [get_ips clk_wiz_0] -log ip_upgrade.log

Upgrading 'clk_wiz_0'

INFO: [IP_Flow 19-3422] Upgraded clk_wiz_0 (Clocking Wizard 5.3) from revision 1 to revision 3

INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_0'...

INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj/ip_upgrade.log'.

export_ip_user_files -of_objects [get_ips clk_wiz_0] -no_script -sync -force -quiet

convert_ips [get_files C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci]

INFO: [filemgmt 56-106] Converting IP 'clk_wiz_0' into core container format.

INFO: [filemgmt 56-101] Creating core container 'C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0.xcix' for IP 'clk_wiz_0'

export_ip_user_files -of_objects [get_files C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci] -sync -lib_map_path

  1. -force -quiet

set_property coreContainer.enable 1 [current_project]
 

2. Build the Project

I then executed generate Bitstream

Bitstream generation successful

Synthesis completed with 51 warnings.

Implementation completed with 3 warnings

DRC violations 1 warning

No errors

3. Program the Board

Hardware target was selected

Multi-color LED is working.

Success?

 

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Hi @BeamPower,

It looks like you ran the cd command for the GPIO demo rather than the OOB demo; as I mentioned on your other thread, I'm not certain why the GPIO demo is occurring so I've asked the creator of that project for some feedback on it. 

The "User" project is the Out of the Box project, but it is mislabeled in the tutorial (I think it used to be called the user project while it was still being developed); I will make sure that name gets fixed. 

I went through the out of the box demo on Vivado 2016.4 and was able to successfully generate the bitstream without any issues (although it did take significantly longer since the project is using MicroBlaze and it was my first time generating the bitstream for that project). I don't have a CmodA7 available to me at the moment though so I am not able to confirm that the project works as expected at the moment.

Let me know if you run into any problems.

Thanks,
JColvin

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Uh oh... I might have my projects mixed up.

But I tried moving forward.

The UART seems to show signs of life.

When I reprogram the board, I get some text on the COM6 serial port terminal (TeraTerm).

CMOD A7 GPIO/UART DEMO!

Also button presses were detected.

CMOD A7 GPIO/UART DEMO!

Button press detected!

Button press detected!

Button press detected!

Button press detected!

I don't understand the next few steps.

Didn't I already program the FPGA in step 3 above?

4. Export to SDK

I tried to export to SDK, but I got an error.

Cannot Export Hardware

The hardware handoff file (.sysdef) does not exist. It may not have been generated
due to:
1. A bitstream might not have been generated. Generate Bitstream and export again,
or do not request a bitstream to be included in export.
2. There are no block design hardware handoff files. Check the vivado log messages
for more details.

So I tried to generate the bitstream again.

But it seems to run on and on.

Vivado Commands

  • Synthesis

  • Implementation

  • Design Initialization

  • [filemgmt 56-147] Overwrite of existing file isn't enabled. Please specify -force to overwrite file [C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj/GPIO.runs/impl_1/.Xil/Vivado-5392-DESKTOP-7CSAO6T/clk_wiz_0/clk_wiz_0.dcp]

  • [Vivado 12-2489] -input_jitter contains time 0.833330 which will be rounded to 0.833 to ensure it is an integer multiple of 1 picosecond ["c:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xdc":57]

Where do I enter the -force command?

I tried to enter it on the Bitstream settings tab, but that did not help.

5. Import the SDK files

6. Program the FPGA

4. Run the Project (should this be step 7?)

 

Maybe best to start over from square 1.

 

 

 

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