Cmod A7 GPIO Demo errors

[BeamPower]

Hello Digilent,

I went to a different PC and was able to slug my way through the first tutorial:
            Cmod A7 - Getting Started with Microblaze

I got some output on the TeraTerm terminal which was mildly satisfying.

Next I stepped into the second tutorial.
            Cmod A7 GPIO Demo

First of all, it isn’t clear if you’re supposed to leave Vivado with the project from Tutorial 1 still loaded?
Or close down Vivado and start with a fresh GUI?
Anyway, I tried both ways.
Neither seems to work.
I have attached a detailed record of what I did, but for some reason I’m getting some errors and can’t move forward.

At my new location, I’m using Vivado 2016.4 and all the requisite software.
I'm following the tutorial step-by-step.
I'm getting implementation errors.

A summary of errors is as follows:
Implementation (2 errors, 1 critical warning)

Design Initialization (1 CRITICAL WARNING)

[Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267]

Opt Design (2 ERRORS)

[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of type 'inst_clk/clk_wiz_0' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

 

Is this salvageable?

A detailed listing is in the attachment.

 

 

20170427 notes tutorial 2 detailed.docx

[JColvin]

Hello @BeamPower,

From my understanding you would be able to either work from the existing Vivado environment (it would ask you if you want to close out the existing project) or work from a fresh GUI without issues. But, I ran through the tutorial (for the Cmod A7 35t version) on my own Vivado 2016.4 and received the same errors that you did, so I have contacted the creator of this project and have asked them to help explain the proper way to go through this tutorial/correct it. I do not know if they are in the office today though and Digilent is closed on the weekends, but I'm hoping for an easy solution (as I imagine you are as well). I'll let you know if I get any updates.

Thanks,
JColvin

[AndrewHolzer]

Hi BeamPower,

I've worked on the project you are trying to use. The error you are seeing arises because the clk_wiz IP block is outdated and needs to be upgraded. Thankfully this is easy to do within Vivado. What you need to do is open up the GPIO project, and underneath tools git Report>Report IP Status. This will open a new tab at the bottom of your screen that shows any IP that is being used by the design. The status for the clk_wiz should say that it needs to be upgraded, so check the box next to clk_wiz, and then Upgrade Selected should become active. Click that, and if you see a confirmation that asks you to use Core Containers, make sure you select that option that doesn't use them. After that, you should be asked if you want to generate new output products, and you can do so. Once that is completed, give a shot at generating the bitstream. 

I've updated the online repositories to contain the updated clk_wiz ip cores. Let me know how everything works out for you!

Regards,

AndrewHolzer

[BeamPower]

Thanks AndrewHolzer. I tried that upgrade on the Out of Box Demo and it seemed to work there.

I'll have to try it with this GPIO Demo project.

You would think Digilent would review their tutorials?

How many people get frustrated with this stuff and quit?

Thanks again.

[jpeyron]

Hi @BeamPower,

Thank you for the feedback. I'm sorry for the frustration/inconvenience that this has caused. I have passed your concerns on to the appropriate people.

thank you,

Jon