CPLD Cool Runner II Clock

[pamcheese]

I am trying to implement a simple JTAG chain in a Cool Runner II development board. I am taking various TDI and TDO signals and routing them in the CPLD depending on what FPGAs are powered on. I see that the CMOD CPLD board provides headers for the clock pins but no actual clock. Can I run a design without a clock if it's just simple switches inside the CPLD to interconnecting TDI and TDO signals?

[jpeyron]

Hi @pamcheese,

Here is a link to our learn page that have some basic switch connecting to a led in verilog using a different board so you would need to use different pins in the ucf. here is our resource page that have some demo project available on the bottom for reference.

cheers,

Jon

[D@n]

@pamcheese,

Why not use the TCK signal for your clock?

Dan