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Ethernet constraints on ARTY


db12321

Question

I followed the ARTY Microblaze server tutorial and was able to get it working. However I noticed that it does not use any input or output delay constraints. I was trying to understand how it is being designed so that these constraints are not needed as well as how to add the constraints so I can check the timing of those timing paths

 

On receive side:  

If I am reading the PHY datasheet correctly the RXD data line transitions are centered at the falling edge of the 25 MHz RX_CLK with but possibly varying from 10ns to 30ns after the rising edge of the clock. a quarter period of the clock.So if I understand this correctly the constraints would be for each pin something like:

set_input_delay -max 30 -clock [get_clocks rx_clock] [get_ports RXD[1]]

set_input_delay -min 10 -clock [get_clocks rx_clock] [get_ports RXD[0]]

Is this the correct way to constrain these?

 

The Ethernetlite MAC in the reference design appears to handle the design by:

1.       Delay the RXD data inputs with a ZHOLD_DELAY block.

2.       Put the RX_CLK is put onto a global clock buffer

3.       latch the output of the ZHOLD_DELAY with the global clock into IOB FFs on the rising edge of the clk.

Is these a reason that this would be guaranteed to work without the clock constraint?

 

Any comments would be much appreciated

Thanks!

 

 

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