Zybo audio codex setup

[zoggx003]

I am currently trying to setup the ssm2603 audio codex on the zybo board to output audio, with a purely rtl design. I am having issues setting up the audio codex via i2c. I am wondering about how you should send the address information to the audio codex to initialize the setup registers. Below is an RTL state machine of how I am trying to write the register values to the codex. Can someone verify that this is the correct way to address the registers? I am unable to get anything out from the audio codex currently, and I don't think my initialization is working.

 

 

always @(*) begin
        next_state = IDLE;
        address    = 7'h0F;
        data       = 8'hFF;
        case(state)
            IDLE: begin
                start      = 0;
                address    = 7'h0F;
                data       = 8'hFF;
                next_state = (setup_audio_codex) ? WR_POWER_MGNT : IDLE;
            end
            WR_POWER_MGNT: begin
                start      = (busy) ? 0 : 1;
                address    = 7'h06;       //power management
                data       = 8'b00000111; //PWROFF,CLKOUT,OSC,OUT,DAC,ADC,MIC,LINEIN
                next_state = (ready) ? WR_DIG_AUDIO_IF : WR_POWER_MGNT;
            end
            WR_DIG_AUDIO_IF: begin
                start      = (busy) ? 0 : 1;
                address    = 7'h07;       //digital audio I/F
                data       = 8'b00000010; //BCLKINV,MS,LRSWAP,LRP,WL,FORMAT
                next_state = (ready) ? WR_DIG_AUDIO_PATH : WR_DIG_AUDIO_IF;
            end
            WR_DIG_AUDIO_PATH: begin
                start      = (busy) ? 0 : 1;
                address    = 7'h05;       //digital audio path
                data       = 8'b00000000; //HPOR,DACMU,DEEMPH,ADCHPF
                next_state = (ready) ? WR_ANA_AUDIO_PATH : WR_DIG_AUDIO_PATH;
            end
            WR_ANA_AUDIO_PATH: begin
                start      = (busy) ? 0 : 1;
                address    = 7'h04;       //analog audio path
                data       = 8'h00010010; //SIDETONE_ATT,SIDETONE_EN,DACSEL,BYPASS,INSEL,MUTEMIC,MICBOOST
                next_state = (ready) ? IDLE : WR_ANA_AUDIO_PATH;
            end
        endcase
    end 

 

[jpeyron]

Hi @zoggx003,

Unfortunately, I have not used the codec with just verilog/vhdl and we currently do not have a demo or tutorial that uses the audio codec of the Zybo in verilog/VHDL. We do have a demo Here with tutorial that uses the audio codex but uses SDK as well as IP's. here is a thread that talks about the audio codec. Here is an Instructable for using the audio codec and the zybo but the same situation.  I did find a vhdl example of using a different codec(zedboard) that you might be able to use as a reference here.

cheers,

Jon