hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values



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Hi @[email protected],

Welcome to the forum! I moved your thread to a section that would get viewed by more fpga experienced forum members. I have not worked with md5 so i'm sure how much help i would be. I have reached out to other forum moderators to see if they would have any input for you. Can you attach the errors you are getting.



Edited by jpeyron
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Hello !! @jpeyron 

yeah actually its  a simulation error. there is some bug in my rtl . I am unable to find the error hence thought this would be a better place to ask .

while implementing md5, since the input message is greater than what the md5 accept as input, for the first 64 rounds it produces proper abcd values . For second rounds,the abcd value are calculated wrong due to which the whole hash value for the md5 input goes wrong. I hope I tried to answer your question


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@[email protected],

Try building your project with Verilator.  On a linux machine, just type "verilator -cc <toplevel-verilog-filename>".  Even if you don't want to simulate using Verilator, the compiler within Verilator can be used to find a lot of bugs.  (For example, you are missing a ; after msg_last.)  I'd produce the full list of bugs found for you, but ... you didn't post all the files to your design, hence Verilator is breaking because it cannot find pancham.h.


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hello here is the md5.h file and the top module through which input is applied 

module top;

reg clk;

reg rst;

reg [0:511] m_in;

reg [0:12] m_in_w;

reg m_in_val;

reg m_first;

reg m_last;

wire [0:127] m_out;

wire m_out_val;

wire ready;

wire final_op;

//////// instantiation of module md5 //


clk =1'b0;

always # 5 clk = ~ clk;

initlal begin 

rst = 1'b1;

m_first = 1'b0'

m_last = 1'b0;

# 12;

rst = 1'b0;


///////////// input message ///

inital begin 

m_in_val = 1'b0;

wait (!rst & ready )

#10 $ display ("---------MD% TEST 0-----------")

m_in = "ponmkljihgfedcbaponmkljihgfedcbaponmkljihgfedcbahgfedcbahgfedcba";

m_in_w = 512;

m_in_val = 1'b1;

m_first = 1'b1;

m_last = 1'b0;


m_in_val = 1'b0;

m_first = 1'b0;

wait (m_out_val)

if (m_out == 128'hF94980206BA2F6E126C27B32D77DC39F )

$display ("MD5 TEST 0 : PASSED");

the output i get is only upto fd2e5c919c8ecadf362c7f1abc959753 and the further 64 rounds gives me wrong output 


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