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Tickstart

Something simple is apparently impossible. Incr/decr number.

Question

Hi, I'm just beginning with FPGA's, I bought a Basys 3 this past tuesday.

I'm trying to increment a 4-bit value with the on-board Up-button and decrease it with the Down-button. What is a straight forward way of doing this?? I've tried to get this to work for the last two days. The buttons are debounced, so that's not an issue.

I've tried keeping the value in a signal vector and depending on which button is pressed, add a one or add a two's complement -1. The adding is done with a 4 bit adder I built, which works.

 

I'm sort of new to VHDL and digital design so any useful tips or hints or general advice are very much appreciated.

Instead of getting 1, 2, 3, 4, 5, 6 etc when pressing the Up button, I get a very weird pattern.. See attached photo (the arrows were meant to show that the pattern repeated itself after a number of presses).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity btn_map is
    Port ( btnD, btnU : in STD_LOGIC;							--btnU/D stands for up/down
           key : out STD_LOGIC_VECTOR (3 downto 0));
end btn_map;

architecture Behavioral of btn_map is

component trig_4b_Adder is
    Port ( clk : in STD_LOGIC;			--I modified the adder with some D-flops to not create a combinatorial loop (hence the clk)
           c, y : in STD_LOGIC_VECTOR (3 downto 0);				--c/y are the two 4-bit inputs to the adder
           s : out STD_LOGIC_VECTOR (3 downto 0));				--s = result
end component;

signal val, add_sub, new_key : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal trigger : STD_LOGIC := '0';		-- clock for the adder, "keypressed"

begin

    Adder: trig_4b_Adder port map(clk => trigger, c => val, y => add_sub, s => new_key); -- add_sub is either the +1, -1 or 0
    
    process(btnD, btnU)
        variable minus : STD_LOGIC_VECTOR (3 downto 0) := "1111";
        variable plus : STD_LOGIC_VECTOR (3 downto 0) := "0001";
        variable zero : STD_LOGIC_VECTOR (3 downto 0) := "0000";
        begin
            if btnD = '1' then
                add_sub <= minus;
            elsif btnU = '1' then
                add_sub <= plus;
            else
                add_sub <= zero; -- (sub zero lol)
            end if;
        end process;
                               
    trigger <= btnU or btnD;		-- start the adder
    val <= new_key;	-- I want to save the result from the adder till next clock cycle	-- these two lines of code feel bad for some reason,
    key <= new_key; -- key is the output from this module					-- like my design is inherently flawed somehow..
    
end Behavioral;

 

IMG_20170422_040209832.jpg

Edited by Tickstart

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@Tickstart,

Can I try to answer your question, "Why does it need to be clocked?"

Your count signal is 4-bits wide.  When you wish to increment this, there's an "equation" or "logic" that needs to take place for all 4 bits.  This function depends upon inc, dec, and the previous counter--so it is roughly a six bit equation.  The problem you have without clocking is that some of those bits will be ready before others.  Sure, they all require one LUT, but routine between them will be different.  The earlier bits will then get used in the equation for the later bits and thus the inputs will not be stable until all of the outputs are determined. 

So ... what results will you expect from a function whose inputs are changing while the function is being evaluated?

Dan

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2 hours ago, D@n said:

So ... what results will you expect from a function whose inputs are changing while the function is being evaluated?

 

Well yeah, that makes sense. But I have some modules which are not clocked (combinatorial..?) nested into the other ones, how do you know when to clock and so on? A regular AND-expression is not clocked for instance but I never hear people complain about that.. Not exactly sure how to keep track of when to clock or not, surely there must be some key insight I'm missing.

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@Tickstart,

The difference between what you proposed above and what you've seen in the past is sometimes called a "logic loop".  In your proposal above, you have logic depending upon itself with no clock.  (This is bad)  In the logic  you've seen before, everything could eventually be traced back to clocked logic somewhere.  The distance between the final piece of logic and the clock that started it off determines the minimum clock period (maximum clock rate) for your board.

Dan

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Dear @Tickstart

I am afraid you are getting confused with multiple points of view. Let me add one more.

FPGAs are used as event driven machines. They produce output based on combination of inputs and these outputs change when there is change on input(s). It can be completely asynchronous machine if you don't need time stimulus. Then there is no need for clock. If your design have regular repetitive event then a clock is your help. Clocks a needed also for generating of signals, communication, and implementing delays.  In VHDL many processes have clock in a list of stimuli but it depends on its purpose. It is necessary for synchronization only.

Events in many control systems are random and the beauty of FPGA that they can respond almost immediately as oppose to clocked processor based controller. The latest industrial PLCs are constructed on FPGAs to achieve fast and deterministic response.

Good luck!

P.S. It should be mentioned that VHDL has operators for simulation only. They are not synthesizable, for example "wait". Clock driven counter is used instead for the implementation.

Edited by Notarobot

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Some pointers to absolute beginners in FPGA development.

1. FPGA development using VHDL or Verilog isn't the same as software development.  Using an HDL to express logic in an FPGA is Computer Aided Digital Design. The place to start is understanding the basic concepts of digital design. Take a course in digital design. Read a book about digital design. Using an HDL for logic synthesis is more complicated than using a computer language like C... there are a lot more things that have to be taken into consideration.

2. Once you've grasped the concepts of digital design you're ready to learn Verilog or VHDL in the context of logic synthesis. In the beginning you don't have to understand how a synthesis tool interprets your HDL code and ends up with a configuration file that programs an FPGA. You DO have to understand all of the elements of the HDL that's in your code in the context of digital logic.

3. Once you've grasped the basics of digital design and using an HDL to do digital design you are ready to understand the code for an entity or module written by someone who does. Then you're ready to understand the HDL in a testbench meant to verify that code. The you can learn how to use a simulator to verify the HDL.

4. Once you gotten to this point you are ready to write code for your first module. The very next step is to write a testbench for that module, simulate it and see what's going on. Verification is part of the HDL design process. Trying to do one without the other is just silly.

5. I you ask for help and someone gives it to you then you are obliged to at least try and follow their instructions. If their instructions aren't helping then you should find help from someone else. Simply ignoring instructions is an insult to you and anyone trying to help you. It is arrogant to think that you can use a language that you know that you don't understand and continue to try and get useful results by writing code. The verification step is helpful in finding errors in syntax, timing and design concept. It isn't a cure for trying to use a language that you don't understand.

I post this more explicit rehash of what I've already said in this thread because I suspect that @Tickstart isn't a real person but a computer simulation... perhaps Yahoo trying to get into IBM's Watson space. A lot of things would start making sense to me if this is true.

 

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