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Arty Z7: Unable to run examples


climblinne

Question

I tried to get the samples "HDMI_IN" & "HDMI_OUT" running with Vivado 2016.4.

First there is no top module name set, when generating the project file. After fixing this, there are unspecified ports.

ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 7 out of 145 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: HDMI_DDC_scl_i, HDMI_DDC_scl_o, HDMI_DDC_scl_t, HDMI_DDC_sda_i, HDMI_DDC_sda_o, HDMI_DDC_sda_t, HDMI_HPD_tri_i[0].

It would be nice, to have some working examples, when starting with a new board...

Thanks!

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2 answers to this question

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Hi Jon,

I have missed the not working git submodule call, when I downloaded the sources with git.

The git submodule reference to the "http" instead of "https" address of the library, so it is not able to download the library. Github is not supporting "http" anymore!

Also I used the Vivado Tcl Shell (commandline) instead of the Vivado Shell inside the Vivado UI, which lead to a wrong project file generation.

Thanks,

climblinne

 

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