Adding a input delay to a port

[joemost]

Hi eveyone,

I have an Input (just connected to a switch on a basis 3 board) that I am trying to add a 20 ns delay to. I have been searching around online trying to exactly figure out how to do that when adding into the constraints file.

 

I tried something like this:

set_property PACKAGE_PIN W5 [get_ports clk_out1]                            
    set_property IOSTANDARD LVCMOS33 [get_ports clk_out1]
    
create_clock -period 20.000 -name clk [get_ports clk_out1]
set_input_delay -clock clk -max 12.000 [get_ports SW15]
set_input_delay -clock clk -min 1.000 [get_ports SW15]    

 

with a 12 second nanosecond delay.. but I can't seem to figure it out.. can anyone explain to be how the syntax of this works? I can't figure out the max and min and how I could set this delay to the positve edge of the input on this chip

(In this case in SW15 is the input port)

 

 

[D@n]

@joemost,

The clock descriptions within the constraints file are designed to tell Vivado about the hardware you have.  In the case of the Basys3, you have a 100MHz clock.  While this clock can be adjusted within the FPGA to create new clocks based upon this one, that adjustment takes place within the FPGA and your FPGA design (Verilog/VHDL) and not within the XDC constraints file.

As a beginner, you should probably make sure the format of your constraints file roughly matches the master constraints file, save for two basic changes: 1) you can change the names of various pins to match your design, and 2) you can comment or uncomment constraints that are being used (or not).

Ok ... that's a little simplistic and there are more things you can do with a constraints file, but you can't change the characteristics of what hardware is actually connected to your device.  It doesn't work that way.

Now, to your problem: you would like to delay something by 20ns.  The easiest way to do this is with the clock. Each clock tick from the Basys3 board is 10ns, so clocking something within your design twice should cause it to delay between 20 and 30 ns.  If this uncertainty is to large, then use your clock to create a faster clock using a clock management tile using either a PLL or Digital Clock Manager (DCM).  With no logic involved, you should be able to get up to nearly 2.5ns resolution, although I've never actually tried and gotten things to run that fast.

Other methods of delaying inputs involve using the IDELAY Xilinx primitive.  This primitive is designed to achieve picosecond delay amounts, so it's probably going to be much to large for what you want.

Dan