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Paul_kimelman

Board Support File Wiki needs to be updated for 2016.4

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I followed the directions on how to add the Diligent boards to Vivado for 2015 and later. I have 2016.4 and it did not work. You have to now go to board_parts and then Artix7 and then put the board files (that correspond to Artix) to make this work. It gives worthless errors if you do anything else.

Edited by Paul_kimelman
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Hi @Paul_kimelman,

Which board are you using? It looks like the Arty-Z7-20. When you created your project are you sure you chose the Arty-Z7-20 and not the Arty-Z7-10? When setting up the project do you have the boards shown in the screen shot below?  I just completed a basic hello_world styled project attached below with no issues. I replaced the board_files here C:\Xilinx\Vivado\2016.4\data\boards\board_files so that the folder contents looks like the attached screen shot.  Please take a screen shot of your project settings like the below screen shot.

cheers,

Jon

arty_z7_20.zip

arty_z7_board_files.jpg

arty_z7_board_files_1.jpg

arty_z7_board_files_2.jpg

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There was never a board_files under boards under data. There were board_parts and board_schemas and a file called board_interface_preferences.xml. But no board_files. I added board_files and it did not like it (I get invalid file warnings on each file). So, I went to board_parts and it is organized as parts and then boards under that. I added the arty board under Artix7 and it then it started showing all of the boards (including the ones in my added board_files). But, it does not show the arty-z7-10 and -20 ones only the arty one by itself. I do not know why. Any ideas? I show it below.

This is bad because arty is not sufficient I guess as the SDK tool complains when I try to load the bitstream with yet another outrageously useless error (no details, nothing about what it wants or what it thinks I have):

13:04:25 INFO    : Connected to target on host '127.0.0.1' and port '3121'.

13:04:53 INFO    : Connected to target on host '127.0.0.1' and port '3121'.

13:04:53 INFO    : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 0' command is executed.

13:04:53 ERROR    : bitstream is not compatible with the target

 

Thanks, Paul

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HI @Paul_kimelman,

If there was not a folder called board_files under boards then add the folder there like the screen shot below. Inside the folder board_files should look like the attached screen shot. Make sure that you first fully unzip the vivado-board folder outside of the download folder then copy or cut the individual board folders and put them here C:\Xilinx\Vivado\2016.4\data\boards\board_files\. you might need to be in admin to be able to do this. When you go to make a new project you should see what is in the above screen shot with the board selected. You need the specific board files for the arty-z7-20 to have it work. it must look like attached screen shot of boards from vivado. Please take screen shots of your folders from here C:\Xilinx\Vivado\2016.4\data\boards\board_files\

cheers,

 

Jon

arty_z7_board_files3.jpg

arty_z7_board_files.jpg

arty_z7_board_files_1.jpg

Edited by jpeyron

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I did that from the start. I unzipped in one place and then copied the file board_files directory tree over. The screenshots are below. I notice the ones that do not show up do not have a mig.prj file whereas the ones that do seem to.

Screen Shot 2017-04-13 at 3.29.40 PM.png

Screen Shot 2017-04-13 at 3.29.52 PM.png

Screen Shot 2017-04-13 at 3.30.16 PM.png

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If I need to uninstall Vivado and re-install and I can. This is very frustrating and I would rather be operational - so if you think this is just Vivado being messed up, I can try to reinstall it. It modified my free Vivado install for the Arty board and that may have messed things up - Xilinx tends to get a lot of this wrong.

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I am thinking Vivado is the problem. Xilinx never seems to be able to develop tools that are reliable if you do anything different. i upgraded to the Design edition for this board and it probably messed it up. I will uninstall and reinstall to see if that fixes it :-(

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Sigh. No joy. I completely uninstalled all parts of Vivado and made sure it was gone including any directories it was using. I then installed it clean from the design edition and applied the license file that was saved from the voucher. I then went to your zip and the "new" directory and copied over the files under board_files. The new install had a board_files with one sub-folder and I pasted in your files. They are all under board_files. I then (and only  then) started Vivado. I did create a project and the board list only shows Arty and not the 2 others. That is, it is similar to what I showed before (less files since I did not take Kintex and the like when installing). So, I am at a loss as to what to do or why you see these. Are you sure you used the ones from your GitHub that are there now? That is, I got them from the instructions at: https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 and the zip came from: https://github.com/Digilent/vivado-boards/archive/master.zip

Maybe you have an older/different one?

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Hoping that I could at least get started with an example, I downloaded the Microblaze base system example from GitHub. It appears that it cannot just be run in Vivado 2016.4. See what it says:

ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.4> of Vivado. Please run the script in Vivado <2015.4> then open the design in Vivado <2016.4>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
ERROR: [BD 5-229] Please open or create a block design first.

If that error is valid, you might want to update it since you cannot even get 2015.4 anymore as far as I know. It also seems to make assumptions about the board given warnings, but I cannot tell. Anyway, thought I would mention this.

cd Y:/Documents/proj/test_arty/Arty-master/Projects/BSD/proj/
source ./create_project.tcl
# if {[info exists ::create_path]} {
#     set dest_dir $::create_path
# } else {
#     set dest_dir [pwd]
# }
# puts "INFO: Creating new project in $dest_dir"
INFO: Creating new project in Y:/Documents/proj/test_arty/Arty-master/Projects/BSD/proj
# set proj_name "bsd"
# set origin_dir ".."
# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
# set src_dir $origin_dir/src
# set repo_dir $origin_dir/repo
# create_project $proj_name $dest_dir
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/Documents/proj/Xilinx/Vivado/2016.4/data/ip'.
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects $proj_name]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "board_part" "digilentinc.com:arty:part0:1.1" $obj
WARNING: [Project 1-153] The current project part 'xc7a50tcsg324-1' does not match with the 'DIGILENTINC.COM:ARTY:PART0:1.1' board part settings. The project part will be reset to 'DIGILENTINC.COM:ARTY:PART0:1.1' board part.
INFO: [Project 1-152] Project part set to artix7 (xc7a35ticsg324-1l)
# set_property "simulator_language" "Mixed" $obj
# set_property "target_language" "VHDL" $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
#   create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
#   create_fileset -constrset constrs_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
# add_files -quiet $src_dir/hdl
# add_files -quiet [glob -nocomplain ../src/ip/*.xci]
# add_files -fileset constrs_1 -quiet $src_dir/constraints
# update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'y:/Documents/proj/test_arty/Arty-master/Projects/BSD/repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
# if {[string equal [get_runs -quiet synth_1] ""]} {
#   create_run -name synth_1 -board_part "digilentinc.com:arty:part0:1.1" -flow {Vivado Synthesis 2015} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
# } else {
#   set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
#   set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
# }
# set obj [get_runs synth_1]
# set_property "part" "xc7a35ticsg324-1L" $obj
# set_property "steps.synth_design.args.fanout_limit" "400" $obj
# set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
# set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
# set_property "steps.synth_design.args.resource_sharing" "off" $obj
# set_property "steps.synth_design.args.no_lc" "1" $obj
# set_property "steps.synth_design.args.shreg_min_size" "5" $obj
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
#   create_run -name impl_1 -board_part "digilentinc.com:arty:part0:1.1" -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
#   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
#   set_property flow "Vivado Implementation 2015" [get_runs impl_1]
# }
# set obj [get_runs impl_1]
# set_property "part" "xc7a35ticsg324-1L" $obj
# set_property "steps.write_bitstream.args.bin_file" "1" $obj
# current_run -implementation [get_runs impl_1]
# puts "INFO: Project created:$proj_name"
INFO: Project created:bsd
# source $origin_dir/src/bd/system.tcl
## set scripts_vivado_version 2015.4
## set current_vivado_version [version -short]
## if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
##    puts ""
##    puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
## 
##    return 1
## }

ERROR: This script was generated using Vivado <2015.4> and is being run in <2016.4> of Vivado. Please run the script in Vivado <2015.4> then open the design in Vivado <2016.4>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
ERROR: [BD 5-229] Please open or create a block design first.
ERROR: [Common 17-39] 'get_bd_designs' failed due to earlier errors.

    while executing
"get_bd_designs"
    invoked from within
"set design_name [get_bd_designs]"
    (file "./create_project.tcl" line 106)

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Hi @Paul_kimelman,

I just checked and they appear to be the same but i am using the vivado board files from here.  If the project was built with microblaze/zynq/ip cores then the version of Vivado matters when using projects. If you have an arty-z7-20 then none of the plan arty projects will work on it .  The projects for the arty-zy-20 are here and are made with Vivado 2016.4. If you are just trying to do an arty project to see vivado/sdk  working then here , here and here are projects updated for Vivado 2016.4. that work with the arty. 

cheers,

Jon

Edited by jpeyron

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How would I know which board I have? I just bought it from  you this week. I cannot find anything that says more than ARTY on the board and on the package and on the invoice. Sticker says Part #410-319

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OK, but please confirm if I have this z7 thing? I cannot find anything that says that. The voucher calls it Artix-7 35T eval kit. The board and packaging all just say ARTY.

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@Paul_kimelman,

There are currently two different Arty boards the Arty(here) and the Arty-Z7-20(here). Based on the Part #410-319 you have the Arty. So even though the other boards are not showing up under boards in Vivado as long as the Arty shows up you can work with the projects here , here and here that are updated for Vivado 2016.4 and work with the Arty. Here is the Arty resource page with tutorials and demos. Here is the Arty template. Here is a non-microblaze Arty template. I will still talk with the more experience engineer to see possible reasons why the other boards are not showing up.

cheers,

Jon

Edited by jpeyron

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OK, so far this is looking promising. I used your link for the BSD project and it loaded without errors. I am doing a generate and will try the SDK. 
Hopefully it will be obvious how to connect an AXI to APB bridge and then install my own logic, which is the last step. If that works, I am golden. 

Thanks for your help.

Regards, Paul

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Be aware that the SDK side did not look or work as the instructions say. That is, https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-microblaze-base-system-design/start which the GitHub refers to. Step 6 does not show the screen as described and then 6.3 does not have the list of projects as shown, only 2 items. The resulting project explorer also looks different as shown - no "demo" but rather bsd and bsd_bsp and system wrapper. As far as I can tell, I followed the instructions to the letter. Seems to work OK, so just FYI.

Also, the link to the Arty page is what got me stuck with 2015.4 things. It should say that in the links. For example, the "Arty general IO demo" says in that page that it is for 2015.4.

Screen Shot 2017-04-13 at 5.42.13 PM.png

Edited by Paul_kimelman

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I just want to share the similar experience with ZYBO. Instead of copying the whole board_files  from Digilent git to Xilinx Vivado folder, I recommend to just copy all folders in the board_files (or the board you have) to the Xilinx folder. The reason is because some boards for example Genesys 2 needs Design edition. If users have Webpack edition, there will be warnings saying no boards found. These warnings won't affect synthesis or implementation in case users build the design on different boards. @sbobrowicz

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