LVTTL or LVCMOS for FMC signals on the Nexys Video board

[Clarissa]

Hello everyone,

I'm migrating my ancient project from the Nexys2 to the Nexys Video, in UCF, the Hirose FX2 signals on the Nexys2 were declared as LVTTL I/O standards, while the FMC signals are declared as LVCMOS in the XDC files provided on the Digilent Resource Center. After doing some researches, I know that LVTTL and LVCMOS differ by their input voltages. In the paragraph of Power Supplies in datasheet of the Nexys Video, il mentions "

An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care
must be taken to disable the regulator first by bringing "VADJ_EN" low, setting "SET_VADJ(1:0)" and enabling the
regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks
(ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF
file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The
provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O
standard for these signals." 

The VADJ power rail requires special attention. It is a programmable voltage rail that powers the FMC mezzanine
connector, user push-buttons, switches, XADC Pmod connector, and the FPGA banks connected to these
peripherals (banks 15, 16).

Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL?

[Notarobot]

Hi Clarissa,

I would suggest to check the effect of the instruction experimentally. It is easy to measure the voltage and then you will be 100% sure if it worked.

Good luck!

[D@n]

@Clarissa,

Yes, it means you can adjust the frequency standard of those pins used on the FMC connector, as well as the power used by the switches, the buttons, and the XADC PMod (not all of the PMods)

FPGA's handle their I/O voltages by bank.  Hence, when you adjust the I/O voltage of a bank, you adjust the I/O voltages of all of the signals on that bank.  This is the reason why you can't just specify a voltage for an I/O pin and expect it to suddenly have that voltage (a common misperception).  The voltage needs to first be set in the voltage rail for the whole I/O bank.  Hence, for most Digilent boards, this I/O voltage is fixed.  This is also true for most of the Nexys Video board, although only one bank's voltage may be adjusted.

If you look across the top of page 10 of the Nexys Video schematic, the Digilent Nexys Video engineer has been kind enough to write above the various I/O banks the voltage standard being used for each bank.  The third I/O bank on that page, labeled as "Bank 15", is the adjustable voltage bank.  If you look further, on page 15, you can see how the SET_VADJx and VADJ_EN lines are connected.  If you'd like, you can even look up the various specifications for the chips that are then used to control that output voltage.

As for the difference between LVCMOS and LVTTL, I would caution you against ascribing the only difference as being to the I/O voltages.  According to Xilinx's SelectIO Resources user guide, starting at page 51, LVTTL is available at 3.3V, whereas LVCMOS is available in 1.2, 1.5, 1.8, 2.5, and 3.3 Volts (p54).  In other words, the difference goes beyond voltage since both LVTTL and LVCMOS can handle 3.3V.

Dan

[zygot]

Clarissa,

Look at the toplevel code for the Nexys Video board in the Differential PMOD Challenge. I address this.

[zygot]

@Clarissa

I was in a hurry to do something else and didn't complete my thought for my last post.

When you use the FMC connector the IOSTANDARD needs to match whatever device is on the FMC mezzanine board. This could be 3.3V, 2.5V or 1.8V. Note that the 12V, 3.3V and Vadj rail are connected to the FMC connector AND FPGA IO banks Vcc pins. You can blow up your FPGA if not careful. Fortunately, Digilent has improved their FMC voltage supply designs though I prefer the Genesys2 design. My point is this; whenever I do a design on the Nexys Video using an FMC mezzanine board I am hyper careful.. like I am when I use a radial arm table saw. This is my basic check-list:

1 Check all FMC signals on the mezzanine board schematic paying special attention to the VCC3V3, VCC12V0, and VADJ pins. I always verify the constraints pins assignments agree with the Nexys Video ( or any FPGA board ) schematic.

2. Find out from the mezzanine board's documentation what the IO voltages are for the device(s) connected to the FMC connector are. This will tell you what Vadj on the Nexys Video board has to be. Understand that ALL pins on all IO banks on the Nexys Video board that use the Vadj  rail have to have compatible standards. This also means that you may have to change IOSTANDARD assignments in your constraints file for other IO pins on the Vadj powered banks that you are using, like buttons, switched, LEDs etc. or bitgen will give you a DRC error. The idea is that the FPGA IO that are connected to anything on the FMC mezzanine card have to be compatible with the mezzanine card devices IO... AND the Vadj voltage has to compatible with that IOSTANDARD. AND all pins on those banks have to be compatible with the Vadj voltage. This isn't quite as complicated as it sounds. If your mezzanine card uses 3.3V differential LVDS then Vadj has to be 3.3V and your IOSTANDARD will be TMDS_33 ( because that's the only 3.3V differential IOSTANDARD available ) Any other pins on the Vadj powered IO banks will be LVCMOS33 if they are single-ended.

3. Once you know what Vadj needs to be you have to go through your constraints file and make sure that all the signals in your toplevel entity port list that are connected to Vadj IO banks are compatible with that voltage. It would be nice if Digilent made this a bit easier. I make a habit of listing the IO bank in the toplevel design comments:

       -- General I/O resources
        btnc                            : in    std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed
        btnd                            : in    std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed
        btnl                            : in    std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed
        btnr                            : in    std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed
        btnu                            : in    std_logic; -- Vadj HR Bank 16 normally '0', '1' when pressed
        sw                              : in    std_logic_vector(7 downto 0); -- Vadj HR Bank 15 or 16
        led                             : out   std_logic_vector(7 downto 0); -- VCC2V5 HR bank 13

4 Check EVERYTHING

5. Check EVERYTHING AGAIN

6 Do something else for 5-6 hours, or better yet wait till the next day and then check EVERYTHING again

7. If you can generate a bitstream for your design without bitgen complaining about incompatible IO assignments you can connect your mezzanine board to your Nexys Video with the power cord disconnected. The power switch on my Nexys Video has failed....

Things get a bit more complicated for the Genesys2 as the Kintex device has HP IO banks and HR IO banks...

The good news that I have is that I've done designs using 5 different FMC mezzanine boards on both my Nexys Video and Genesys2 boards without either of them violating the "NO SMOKING" ban in my lab.

Again, you can check out one way to handle FMC Vadj in my code in the Project Vault Differential PMOD Challenge code.

[Clarissa]

@zygot,

Could you tell me how to configure Vadj voltage? 

More concretely, how can I set VADJ_EN and T_VADJ(1:0)?

[Clarissa]

Just now, Clarissa said:

@zygot,

Could you tell me how to configure Vadj voltage? 

More concretely, how can I set VADJ_EN and T_VADJ(1:0)?

I mean VADJ_EN and SET_VADJ(1:0)

[zygot]

@Clarissa,

You wrote in the original post:"Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL? "

I assume that you're working with an FMC mezzanine card that replaces the old FX2 interface. It's important to follow my previous advice by checking all of the FMC voltage connections that are connected to the logic through this FMC card. In particular make sure that:

- only the Nexys Video board is sourcing the 12V0, 3V3, and VADJ pins. Also that everything connected to these pins is compatible with those voltages.

- any logic connected to the GA0 or GA1 pins is 3.3V compatible

- any logic connected to any of the FMC logic pins is really is LVCMOS33 compatible. LVCMOS33 and LVTTL33 are not exactly the same.

Once you have satisfied yourself that everything is OK then, you would want to do what you have stated above, I use a big counter that stops counting before it rolls over to 0 to time the operations stated in the manual. I assume that you didn't check out the code in the DIfferential PMOD Challenge. I've posted the toplevel module here. You'll want to set set_vadj        <= "11".  Look over the process that controls vcnt. Your implementation will depending on the clock frequency that you are using of course, but I'd suggest that you use my timing as a minimum. You'll want to allow for the power supplies to settle. As far as I know Digilent has never offered guidance on how to follow the instructions in their manual.

There's one aspect of my code that you should note. If areset is asserted VADJ is disabled and the whole procedure is repeated. You may or may not want to do this.

I suggest that you prove to yourself that the VADJ voltage is really working as expected by using an oscilloscope to capture VADJ before connecting your FMC mezzanine card. As written you can check this by asserting areset. Note that the switches and all but the CPU reset button use the VADJ supply ( likely there are more things using Vadj) .... Also note that the CPU reset button is doesn't have any hardware conditioning to correct contact bounce so you may want to debounce CPU reset in you code if that's what's used to assert areset.

If you don't understand anything that I've already stated in this thread you'll have to address specifically.

NexysVideo_SDR_Test.vhd

[zygot]

To anyone who thinks that my answers to this question were way too brief and not verbose enough I offer one more thought. No one has asked what the difference is between LVCMOS33 and LVTTL33. But in the interest of my moving on mentally I'll take a stab at the answer. It's not as simple as one might suppose.

This web page is a nice visual of the basics to take into consideration for connecting to various logic technologies and families: http://www.interfacebus.com/voltage_threshold.html

Now then, I'm one of those old dinosaurs who had to work with a lot of logic families back in the day when logic came in 14 or 16 pin DIP packages. Though the chart referenced above might be confusing it does show the 4 basic specifications to worry about. Clarissa doesn't provide a schematic or mention what devices are connected to her FMC interface but let's assume, for the sake of this discussion,  that it has actual TTL or CMOS devices. For the purposes of whether or not your logic can decide if an input signal is a logic high or low there are minimum and maximum voltages that have to be met for both high and low. If the input signal is not within these ranges the logic can't reliably tell what level the input signal is. All logic families also have minimum, typical and maximum output specifications for logic high and logic low that are guaranteed. So, for the most basic analysis, whatever is driving your logic had better meet the input specifications for your logic inputs. What I've mentioned so far has to do the the DC specifications. in the old days when a lot of logic was in discrete LSI and MSI devices the analysis for whether or not you circuit worked was complicated by things such as temperature variations, supply voltage variations, capacitive loading, etc. When the Schottky logic came out with really fast transition times we had to also consider the signal integrity of the wiring between output and input pins. Now we're talking about AC specifications. Now this isn't close to being a complete lecture on using discrete logic as there is more to consider but perhaps those who are interested will do some investigation on their own.  Texas Instruments has some information as they still manufacture the old stuff.

If Clarissa's interface uses some other components then the data sheet for those devices usually states if the logic inputs and outputs are TTL or CMOS compatible.