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Chao

Zybo board how to print message

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Hi,

I'm new to this forum. I recently bought a Zybo board and try to do some fun staff. 

I went through the "Getting started with zybo" tutorial in resource centre.

In this tutorial, it stated that "print a message when one of buttons is pressed ". I can turn on the switch and also with the corresponding led turned on. But how to print a message?

Thank you for your time and help

Chao

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Hi Chao,

The first Zybo application is a demonstration of two available on the board user inputs:

1) Switches: turning each of four switches should result in turning on corresponding LED;

2) Push buttons: pressing push buttons should result in a message to a user "button # pressed".

You can see C code related to these messages, for example, xil_printf("button 0 pressed\n\r");

The message can be captured and seen via serial (RS232) port connection to your Zybo board. You can use Xilinx SDK or any terminal application for communication with the Zybo.

The easiest way is to use SDK Terminal tab which is located in the bottom of Xilinx SDK window. You will need to click on the icon "+" then specify the port name and 115200 Baud rate. If everything correct you will see push button messages in the terminal window.

In my opinion this is one of the easiest and most useful tools for debugging of C applications. Another great debugging tool given for free is a logic analyzer which allows for tracing FPGA in time.

Good luck!


 

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14 hours ago, Notarobot said:

Hi Chao,

The first Zybo application is a demonstration of two available on the board user inputs:

1) Switches: turning each of four switches should result in turning on corresponding LED;

2) Push buttons: pressing push buttons should result in a message to a user "button # pressed".

You can see C code related to these messages, for example, xil_printf("button 0 pressed\n\r");

The message can be captured and seen via serial (RS232) port connection to your Zybo board. You can use Xilinx SDK or any terminal application for communication with the Zybo.

The easiest way is to use SDK Terminal tab which is located in the bottom of Xilinx SDK window. You will need to click on the icon "+" then specify the port name and 115200 Baud rate. If everything correct you will see push button messages in the terminal window.

In my opinion this is one of the easiest and most useful tools for debugging of C applications. Another great debugging tool given for free is a logic analyzer which allows for tracing FPGA in time.

Good luck!



 

Hi Notarobot,

Thanks for the help, I get the message printed.

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Hi:

I am new for zybo.

when I add IP zynq processor and open the " ZYNQ7 processing system" Re-customize IP window. looks like, there is nothing selected. do I need manully selected some Like Uart1 for Hello world project?

 

Michael

customize IP.docx

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Hi @Michael2018,

Please install the board files. The board files for the Zybo configure the zynq processor. Here is the Installing Vivado and Digilent Board Files tutorial.  Once you have installed the board files to make the hello work project you only need the zynq processor. Make sure to connect the fclk_clk0 to the m_axi_gp0_aclk after running block automation. Then create a wrapper, generate a bitstream, export hardware with bistream and launch sdk. Once sdk is open make a new application with the hello world template, program the fpga anf then right click on the application an run as->launch on hardware(system debugger). I would suggest to use a serisl terminal like tera term and make sure the baud rate is set to 115200 to see the uart-usb communication.

thank you,

Jon

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Hi: Jpeyron

At install zybo board file link, there is two line" Load_features core and  enable_beta_device* " not show the when which I download vivado_ini file. do I need put in this two line message?

 

thank you for your help!

Michael

vivado_ini.docx

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Hi @Michael2018,

The board files configure parts in the zynq processor such as the uart and ddr that are tied directly to the zynq processor. Hopefully the attached image can better describe how the zynq processor is connected.

thank you,

Jon

zynq_processor.png

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Hi: jpeyron

when I select "Hello Word" Templates , I got error message" this application requires a Uart IP in the hardware.

do I need go back to reconfigure the zynq processor?

 

Michael

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Hi Jon

 

I followed you instruction and make new project but I still get same error " This application requires a Uart IP in the hardware." message. 

can you send me a working HELLO project file, I can try my board. to make sure board is working.

where I can get board file B.3

Michael

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Hi: Jon

I updated the Board file to B.3 right now different looking when  I look the zynq IP configuration window.

but when I run at SDK at Hello project, the terminal thing print out;

here some log file:

15:06:19 INFO    : Registering command handlers for SDK TCF services
15:06:20 INFO    : Launching XSCT server: xsct.bat -interactive C:\Data\Project\Hello2\Hello2.sdk\temp_xsdb_launch_script.tcl
15:06:22 INFO    : XSCT server has started successfully.
15:06:22 INFO    : Successfully done setting XSCT server connection channel  
15:06:22 INFO    : Successfully done setting SDK workspace  
15:06:22 INFO    : Processing command line option -hwspec C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper.hdf.
15:07:43 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
15:07:45 INFO    : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo 210279573175A" && level==0} -index 1' command is executed.
15:07:46 INFO    : FPGA configured successfully with bitstream "C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/hello2_wrapper.bit"
15:10:32 INFO    : 'targets -set -filter {jtag_cable_name =~ "Digilent Zybo 210279573175A" && level==0} -index 1' command is executed.
15:10:32 INFO    : 'fpga -state' command is executed.
15:10:32 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
15:10:33 INFO    : Jtag cable 'Digilent Zybo 210279573175A' is selected.
15:10:33 INFO    : 'jtag frequency' command is executed.
15:10:33 INFO    : Sourcing of 'C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/ps7_init.tcl' is done.
15:10:33 INFO    : Context for 'APU' is selected.
15:10:33 INFO    : Hardware design information is loaded from 'C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/system.hdf'.
15:10:33 INFO    : 'configparams force-mem-access 1' command is executed.
15:10:33 INFO    : Context for 'APU' is selected.
15:10:33 INFO    : 'stop' command is executed.
15:10:33 INFO    : 'ps7_init' command is executed.
15:10:33 INFO    : 'ps7_post_config' command is executed.
15:10:33 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
15:10:33 INFO    : Processor reset is completed for 'ps7_cortexa9_0'.
15:10:33 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
15:10:33 INFO    : The application 'C:/Data/Project/Hello2/Hello2.sdk/Hello_ledSwitch2/Debug/Hello_ledSwitch2.elf' is downloaded to processor 'ps7_cortexa9_0'.
15:10:33 INFO    : 'configparams force-mem-access 0' command is executed.
15:10:33 INFO    : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/ps7_init.tcl
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0
loadhw -hw C:/Data/Project/Hello2/Hello2.sdk/hello2_wrapper_hw_platform_0/system.hdf -mem-ranges


  1. configparams force-mem-access 1
    targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0
    stop
    ps7_init
    ps7_post_config
    targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0
    rst -processor
    targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0
    dow C:/Data/Project/Hello2/Hello2.sdk/Hello_ledSwitch2/Debug/Hello_ledSwitch2.elf
    configparams force-mem-access 0
    ----------------End of Script----------------

15:10:33 INFO    : Memory regions updated for context APU
15:10:33 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
15:10:33 INFO    : 'con' command is executed.
15:10:33 INFO    : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279573175A"} -index 0
con
----------------End of Script----------------

15:10:33 INFO    : Launch script is exported to file 'C:\Data\Project\Hello2\Hello2.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_hello_ledswitch2.elf_on_local.tcl'


please tell me what is not right.

 

Michael

 

 

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Hi @Michael2018,

I got my board files from hereHere is a completed hello world project for the Zybo using Vivado 2017.4.  I have attached some screen shots below.The zynq processor screen shot is the zybo board file default.

thank you,

Jon

 

zybo_default_zynq_processor.png

zybo_sdk_hello_world.jpg

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Hi: Jon

every thing is working now . just board file is in correct. After I change it B.3 version. It work fine.

thank you very much for your help! specially thank you for your quick responds.

 

Sincerely,

Michael

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Hi: Jon

when I create a new design with zynq processor I got warring messaage :

validate_bd_design
[PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values.

can you tell me what is wrong?  and How to fix it.

 

thank you very much

 

Michael 

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when I ceate a warrper file I got warring message:

Analysis Resultssources_1[filemgmt 20-1318] Duplicate Design Unit 'zynq_interrupt_system_ps7_0_axi_periph_0' found in library 'xil_defaultlib'
sim_1[filemgmt 20-1318] Duplicate Design Unit 'zynq_interrupt_system_ps7_0_axi_periph_0' found in library 'xil_defaultlib'
zynq_interrupt_systemvalidate_bd_design
[PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values.


do I need fix it?

How  to fix it

 

Sincerely,

Michael

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Hi @Michael2018,

I just made a similar project based on you block design and i did not get these warnings. Did you use the board file for the zybo when making this project? Did you alter anything in the zynq processor? You might benefit from the zynq book  which has the book available for free when downloading.

thank you,

Jon

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Hi: Jon

I did not do any modification for processor IP. just default set up.

I will take a look the zynq book and hope find some clue.

thank you for your help and you have a greate weekend!

 

Michael

 

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