clock mismatch in IP integrator

[shashi]

HI there, 

I have a simple HLS design which I exported as an IP Core to implement on my target. But I get the following error when I go ahead interconnecting the IP cores. Does anyone have any idea as to how I can work around this obstacle? 

I even tried changing the frequency of the ports, but the fields are inactive.

 

 [BD 41-237] Bus Interface property FREQ_HZ does not match between /matrixmul_0/INPUT_STREAM(100000000) and /axi_dma_0/M_AXIS_MM2S(200000000)
 [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_dma_0/S_AXIS_S2MM(200000000) and /matrixmul_0/OUTPUT_STREAM(100000000)

 

 

[jpeyron]

Hi @shashi,

I do not have much experience with HLS designs but I did find at the end of this thread that deals with the frequency issues here something that might have a solution. They added a clk convertor modules to sync up the exchange between the two modules.

thank you,

Jon